tb.h revision 12855:588919e0e4aa
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311723Sar4jc@virginia.edu  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
411723Sar4jc@virginia.edu  more contributor license agreements.  See the NOTICE file distributed
511723Sar4jc@virginia.edu  with this work for additional information regarding copyright ownership.
611723Sar4jc@virginia.edu  Accellera licenses this file to you under the Apache License, Version 2.0
711723Sar4jc@virginia.edu  (the "License"); you may not use this file except in compliance with the
811723Sar4jc@virginia.edu  License.  You may obtain a copy of the License at
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1011723Sar4jc@virginia.edu    http://www.apache.org/licenses/LICENSE-2.0
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1211723Sar4jc@virginia.edu  Unless required by applicable law or agreed to in writing, software
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2111723Sar4jc@virginia.edu
2211723Sar4jc@virginia.edu  tb.h --
2311723Sar4jc@virginia.edu
2411723Sar4jc@virginia.edu  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
2511723Sar4jc@virginia.edu
2611723Sar4jc@virginia.edu *****************************************************************************/
2711723Sar4jc@virginia.edu
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2911723Sar4jc@virginia.edu
3011723Sar4jc@virginia.edu  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
3111723Sar4jc@virginia.edu  changes you are making here.
3211723Sar4jc@virginia.edu
3311723Sar4jc@virginia.edu      Name, Affiliation, Date:
3411723Sar4jc@virginia.edu  Description of Modification:
3511723Sar4jc@virginia.edu
3611723Sar4jc@virginia.edu *****************************************************************************/
3711723Sar4jc@virginia.edu
3811723Sar4jc@virginia.edu/* Common interface file for test bench
3911723Sar4jc@virginia.edu   Author: PRP
4011723Sar4jc@virginia.edu   */
4111723Sar4jc@virginia.edu
4211723Sar4jc@virginia.eduSC_MODULE( tb )
4311723Sar4jc@virginia.edu{
4411723Sar4jc@virginia.edu    SC_HAS_PROCESS( tb );
4511723Sar4jc@virginia.edu
4611723Sar4jc@virginia.edu    sc_in_clk clk;
4711723Sar4jc@virginia.edu
4811723Sar4jc@virginia.edu        // Output Reset Port
4911723Sar4jc@virginia.edu        sc_signal<bool>& reset_sig;
5011723Sar4jc@virginia.edu
5111723Sar4jc@virginia.edu        // Output Data Ports
5211723Sar4jc@virginia.edu	sc_signal<int>& i1;
5311965Sar4jc@virginia.edu	sc_signal<int>& i2;
5411723Sar4jc@virginia.edu	sc_signal<int>& i3;
5511723Sar4jc@virginia.edu	sc_signal<int>& i4;
5611723Sar4jc@virginia.edu	sc_signal<int>& i5;
5711723Sar4jc@virginia.edu
5811723Sar4jc@virginia.edu        // Output Control Ports
5911723Sar4jc@virginia.edu	sc_signal<bool>& cont1;
6012808Srobert.scheffel1@tu-dresden.de	sc_signal<bool>& cont2;
6111723Sar4jc@virginia.edu	sc_signal<bool>& cont3;
6211723Sar4jc@virginia.edu
6311723Sar4jc@virginia.edu        // Input Data Ports
6411723Sar4jc@virginia.edu	const sc_signal<int>& o1;
6512808Srobert.scheffel1@tu-dresden.de	const sc_signal<int>& o2;
6612808Srobert.scheffel1@tu-dresden.de	const sc_signal<int>& o3;
6711723Sar4jc@virginia.edu	const sc_signal<int>& o4;
6811723Sar4jc@virginia.edu	const sc_signal<int>& o5;
6911723Sar4jc@virginia.edu
7011723Sar4jc@virginia.edu	// Constructor
7111723Sar4jc@virginia.edu	tb (
7211723Sar4jc@virginia.edu        sc_module_name NAME,
7311723Sar4jc@virginia.edu	sc_clock& CLK,
7411723Sar4jc@virginia.edu
7511723Sar4jc@virginia.edu        sc_signal<bool>& RESET_SIG,
7612222Sgabeblack@google.com
77	sc_signal<int>& I1,
78	sc_signal<int>& I2,
79	sc_signal<int>& I3,
80	sc_signal<int>& I4,
81	sc_signal<int>& I5,
82
83	sc_signal<bool>& CONT1,
84	sc_signal<bool>& CONT2,
85	sc_signal<bool>& CONT3,
86
87	const sc_signal<int>& O1,
88	const sc_signal<int>& O2,
89	const sc_signal<int>& O3,
90	const sc_signal<int>& O4,
91	const sc_signal<int>& O5)
92	  : reset_sig(RESET_SIG), i1(I1),  i2(I2),
93	    i3(I3),  i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2),
94	    cont3 (CONT3), o1(O1),  o2(O2),  o3(O3),  o4(O4),  o5(O5)
95        {
96	  clk(CLK);
97            SC_CTHREAD( entry, clk.pos() );
98	}
99
100  void entry();
101};
102