1 revision 12855:588919e0e4aa 
1/* Common interface file for test bench
2   Author: PRP 
3   */
4
5SC_MODULE( tb )
6{
7    SC_HAS_PROCESS( tb );
8
9    sc_in_clk clk;
10
11        // Output Reset Port
12        sc_signal<bool>& reset_sig;
13
14        // Output Data Ports
15	sc_signal<int>& i1;
16	sc_signal<int>& i2;
17	sc_signal<int>& i3;
18	sc_signal<int>& i4;
19	sc_signal<int>& i5;
20
21        // Output Control Ports
22	sc_signal<bool>& cont1;
23	sc_signal<bool>& cont2;
24	sc_signal<bool>& cont3;
25
26        // Input Data Ports
27	const sc_signal<int>& o1;
28	const sc_signal<int>& o2;
29	const sc_signal<int>& o3;
30	const sc_signal<int>& o4;
31	const sc_signal<int>& o5;
32
33	// Constructor
34	tb (	
35        const char* NAME, 
36	sc_clock_edge& CLK,
37
38        sc_signal<bool>& RESET_SIG,
39
40	sc_signal<int>& I1,
41	sc_signal<int>& I2,
42	sc_signal<int>& I3,
43	sc_signal<int>& I4,
44	sc_signal<int>& I5,
45
46	sc_signal<bool>& CONT1,
47	sc_signal<bool>& CONT2,
48	sc_signal<bool>& CONT3,
49
50	const sc_signal<int>& O1,
51	const sc_signal<int>& O2,
52	const sc_signal<int>& O3,
53	const sc_signal<int>& O4,
54	const sc_signal<int>& O5)
55	  : sc_sync (NAME, CLK), reset_sig(RESET_SIG), i1(I1),  i2(I2),  
56	    i3(I3),  i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), 
57	    cont3 (CONT3), o1(O1),  o2(O2),  o3(O3),  o4(O4),  o5(O5) 
58        {
59	}
60
61  void entry();
62};
63