test.h revision 12855:588919e0e4aa 
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3  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
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6  Accellera licenses this file to you under the Apache License, Version 2.0
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10    http://www.apache.org/licenses/LICENSE-2.0
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12  Unless required by applicable law or agreed to in writing, software
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19
20/*****************************************************************************
21
22  test.h --
23
24  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25
26 *****************************************************************************/
27
28/*****************************************************************************
29
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
32
33      Name, Affiliation, Date:
34  Description of Modification:
35
36 *****************************************************************************/
37
38/* Common interface file for test cases
39   Author: PRP
40   */
41
42SC_MODULE( test )
43{
44    SC_HAS_PROCESS( test );
45
46    sc_in_clk clk;
47
48        // Input Reset Port
49        const sc_signal<bool>& reset_sig;
50
51        // Input Data Ports
52	const sc_signal<int>& i1;
53	const sc_signal<int>& i2;
54	const sc_signal<int>& i3;
55	const sc_signal<int>& i4;
56	const sc_signal<int>& i5;
57
58        // Input Control Ports
59	const sc_signal<bool>& cont1;
60	const sc_signal<bool>& cont2;
61	const sc_signal<bool>& cont3;
62
63        // Output Data Ports
64	sc_signal<int>& o1;
65	sc_signal<int>& o2;
66	sc_signal<int>& o3;
67	sc_signal<int>& o4;
68	sc_signal<int>& o5;
69
70	// Constructor
71	test (
72        sc_module_name NAME,
73	sc_clock& CLK,
74
75        const sc_signal<bool>& RESET_SIG,
76
77	const sc_signal<int>& I1,
78	const sc_signal<int>& I2,
79	const sc_signal<int>& I3,
80	const sc_signal<int>& I4,
81	const sc_signal<int>& I5,
82
83	const sc_signal<bool>& CONT1,
84	const sc_signal<bool>& CONT2,
85	const sc_signal<bool>& CONT3,
86
87	sc_signal<int>& O1,
88	sc_signal<int>& O2,
89	sc_signal<int>& O3,
90	sc_signal<int>& O4,
91	sc_signal<int>& O5)
92	  : reset_sig(RESET_SIG), i1(I1),  i2(I2),
93	    i3(I3),  i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2),
94	    cont3 (CONT3), o1(O1),  o2(O2),  o3(O3),  o4(O4),  o5(O5)
95        {
96	  clk(CLK);
97          SC_CTHREAD( entry, clk.pos() );
98	  reset_signal_is(reset_sig,true);
99	}
100
101  void entry();
102};
103