tb.h revision 12855:588919e0e4aa
11897Sstever@eecs.umich.edu/***************************************************************************** 24130Ssaidi@eecs.umich.edu 31897Sstever@eecs.umich.edu Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 41897Sstever@eecs.umich.edu more contributor license agreements. See the NOTICE file distributed 51897Sstever@eecs.umich.edu with this work for additional information regarding copyright ownership. 61897Sstever@eecs.umich.edu Accellera licenses this file to you under the Apache License, Version 2.0 71897Sstever@eecs.umich.edu (the "License"); you may not use this file except in compliance with the 81897Sstever@eecs.umich.edu License. You may obtain a copy of the License at 91897Sstever@eecs.umich.edu 101897Sstever@eecs.umich.edu http://www.apache.org/licenses/LICENSE-2.0 111897Sstever@eecs.umich.edu 121897Sstever@eecs.umich.edu Unless required by applicable law or agreed to in writing, software 131897Sstever@eecs.umich.edu distributed under the License is distributed on an "AS IS" BASIS, 141897Sstever@eecs.umich.edu WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 151897Sstever@eecs.umich.edu implied. See the License for the specific language governing 161897Sstever@eecs.umich.edu permissions and limitations under the License. 171897Sstever@eecs.umich.edu 181897Sstever@eecs.umich.edu *****************************************************************************/ 191897Sstever@eecs.umich.edu 201897Sstever@eecs.umich.edu/***************************************************************************** 211897Sstever@eecs.umich.edu 221897Sstever@eecs.umich.edu tb.h -- 231897Sstever@eecs.umich.edu 241897Sstever@eecs.umich.edu Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 251897Sstever@eecs.umich.edu 261897Sstever@eecs.umich.edu *****************************************************************************/ 271897Sstever@eecs.umich.edu 281897Sstever@eecs.umich.edu/***************************************************************************** 291897Sstever@eecs.umich.edu 301897Sstever@eecs.umich.edu MODIFICATION LOG - modifiers, enter your name, affiliation, date and 311897Sstever@eecs.umich.edu changes you are making here. 321897Sstever@eecs.umich.edu 331897Sstever@eecs.umich.edu Name, Affiliation, Date: 344961Ssaidi@eecs.umich.edu Description of Modification: 351897Sstever@eecs.umich.edu 361897Sstever@eecs.umich.edu *****************************************************************************/ 371897Sstever@eecs.umich.edu 381897Sstever@eecs.umich.edu/* Common interface file for test bench 397047Snate@binkert.org Author: PRP 408319Ssteve.reinhardt@amd.com */ 417047Snate@binkert.org 428319Ssteve.reinhardt@amd.comSC_MODULE( tb ) 438811Sandreas.hansson@arm.com{ 4410007Snilay@cs.wisc.edu SC_HAS_PROCESS( tb ); 458811Sandreas.hansson@arm.com 468811Sandreas.hansson@arm.com sc_in_clk clk; 478811Sandreas.hansson@arm.com 489850Sandreas.hansson@arm.com // Output Reset Port 498811Sandreas.hansson@arm.com sc_signal<bool>& reset_sig; 508811Sandreas.hansson@arm.com 5110007Snilay@cs.wisc.edu // Output Data Ports 528811Sandreas.hansson@arm.com sc_signal<int>& i1; 537047Snate@binkert.org sc_signal<int>& i2; 548811Sandreas.hansson@arm.com sc_signal<int>& i3; 558811Sandreas.hansson@arm.com sc_signal<int>& i4; 568811Sandreas.hansson@arm.com sc_signal<int>& i5; 578319Ssteve.reinhardt@amd.com 588319Ssteve.reinhardt@amd.com // Output Control Ports 598319Ssteve.reinhardt@amd.com sc_signal<bool>& cont1; 608319Ssteve.reinhardt@amd.com sc_signal<bool>& cont2; 618319Ssteve.reinhardt@amd.com sc_signal<bool>& cont3; 628319Ssteve.reinhardt@amd.com 638319Ssteve.reinhardt@amd.com // Input Data Ports 647047Snate@binkert.org const sc_signal<int>& o1; 658319Ssteve.reinhardt@amd.com const sc_signal<int>& o2; 668319Ssteve.reinhardt@amd.com const sc_signal<int>& o3; 677047Snate@binkert.org const sc_signal<int>& o4; 687047Snate@binkert.org const sc_signal<int>& o5; 698319Ssteve.reinhardt@amd.com 708319Ssteve.reinhardt@amd.com // Constructor 718319Ssteve.reinhardt@amd.com tb ( 727047Snate@binkert.org sc_module_name NAME, 737047Snate@binkert.org sc_clock& CLK, 747047Snate@binkert.org 751897Sstever@eecs.umich.edu sc_signal<bool>& RESET_SIG, 761897Sstever@eecs.umich.edu 771897Sstever@eecs.umich.edu sc_signal<int>& I1, 781897Sstever@eecs.umich.edu sc_signal<int>& I2, 798319Ssteve.reinhardt@amd.com sc_signal<int>& I3, 808319Ssteve.reinhardt@amd.com sc_signal<int>& I4, 818319Ssteve.reinhardt@amd.com sc_signal<int>& I5, 828319Ssteve.reinhardt@amd.com 838319Ssteve.reinhardt@amd.com sc_signal<bool>& CONT1, 848319Ssteve.reinhardt@amd.com sc_signal<bool>& CONT2, 858319Ssteve.reinhardt@amd.com sc_signal<bool>& CONT3, 861897Sstever@eecs.umich.edu 878319Ssteve.reinhardt@amd.com const sc_signal<int>& O1, 888811Sandreas.hansson@arm.com const sc_signal<int>& O2, 898319Ssteve.reinhardt@amd.com const sc_signal<int>& O3, 908319Ssteve.reinhardt@amd.com const sc_signal<int>& O4, 911897Sstever@eecs.umich.edu const sc_signal<int>& O5) 927047Snate@binkert.org : reset_sig(RESET_SIG), i1(I1), i2(I2), 937047Snate@binkert.org i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), 941897Sstever@eecs.umich.edu cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) 951897Sstever@eecs.umich.edu { 964961Ssaidi@eecs.umich.edu clk(CLK); 974961Ssaidi@eecs.umich.edu SC_CTHREAD( entry, clk.pos() ); 984961Ssaidi@eecs.umich.edu } 994961Ssaidi@eecs.umich.edu 1004961Ssaidi@eecs.umich.edu void entry(); 1014961Ssaidi@eecs.umich.edu}; 1024961Ssaidi@eecs.umich.edu