circ48.h revision 12855:588919e0e4aa 
1/*****************************************************************************
2
3  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
4  more contributor license agreements.  See the NOTICE file distributed
5  with this work for additional information regarding copyright ownership.
6  Accellera licenses this file to you under the Apache License, Version 2.0
7  (the "License"); you may not use this file except in compliance with the
8  License.  You may obtain a copy of the License at
9
10    http://www.apache.org/licenses/LICENSE-2.0
11
12  Unless required by applicable law or agreed to in writing, software
13  distributed under the License is distributed on an "AS IS" BASIS,
14  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
15  implied.  See the License for the specific language governing
16  permissions and limitations under the License.
17
18 *****************************************************************************/
19
20/*****************************************************************************
21
22  circ48.h --
23
24  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25
26 *****************************************************************************/
27
28/*****************************************************************************
29
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
32
33      Name, Affiliation, Date:
34  Description of Modification:
35
36 *****************************************************************************/
37
38#include "common.h"
39
40SC_MODULE( circ48 )
41{
42    SC_HAS_PROCESS( circ48 );
43
44    sc_in_clk clk;
45
46    sc_in<bool>         reset;
47    sc_in<bool>         x_ok;
48    sc_in<bool>         y_ok;
49    sc_out<bool>        out_wr;
50    sc_out<bool>        out_sel;
51    sc_out<bool_vector> out_xy;
52    sc_out<bool_vector> diffs;
53
54    void entry();
55
56    circ48( sc_module_name         name_,
57	    const sc_clock&        clk_,
58	    const sc_signal<bool>& reset_,
59	    const sc_signal<bool>& x_ok_,
60	    const sc_signal<bool>& y_ok_,
61	    sc_signal<bool>&       out_wr_,
62	    sc_signal<bool>&       out_sel_,
63	    signal_bool_vector&    out_xy_,
64	    signal_bool_vector&    diffs_ )
65	: sc_module( name_ )
66    {
67          clk( clk_ );
68	  reset( reset_ );
69	  x_ok( x_ok_ );
70	  y_ok( y_ok_ );
71	  out_wr( out_wr_ );
72	  out_sel( out_sel_ );
73	  out_xy( out_xy_ );
74	  diffs( diffs_ );
75	SC_CTHREAD( entry, clk.pos() );
76	reset_signal_is(reset,true);
77    }
78};
79
80
81/*****************************************************************************/
82/**									    **/
83/**  This function is the "clean" behavior (i.e. not written with synthesis **/
84/**  or implementation in mind.  This is a circle generator, that uses an   **/
85/**  algorithmic, interpolating technique.  Origin of circle is fixed to    **/
86/**  point (0,0) 							    **/
87/**  NOTE:  Extra WAIT at end for VGB (requires waits after signal assign)  **/
88/**									    **/
89/*****************************************************************************/
90
91void
92circ48::entry()
93{
94    sc_signed x(4);
95    sc_signed y(4);
96    sc_signed x_end(4);
97    sc_signed y_end(4);
98    sc_signed diff(8);
99    bool first;
100
101    // reset initialization
102
103    out_wr.write( 0 );		// Initialize at time zero ????
104    out_sel.write( 0 );
105
106    // setup counter-clockwise circle generation
107
108    while(true) {  // Reset_loop
109	x_end = 4;
110	x = x_end;
111	diff = 0;
112	diffs.write(diff);
113	y_end = 4;
114	y = y_end;
115	first = true;
116	wait();
117
118        // perform counter-clockwise circle generation
119
120	while(first || (x != x_end) || (y != y_end)) {  // Main_loop
121	    first = false;
122	    diff = diff + 1;
123
124	    if (diff > 1) {
125		if ((x >= 0) && (y >= 0)) {
126		    diff = diff - x - x;
127		    x = x - 1;
128		}
129		else { // else_1_begin
130		    if ((x < 0) && (y >= 0)) {
131			diff = diff - y - y;
132			y = y - 1;
133		    }
134		    else { // else_2_begin
135			if ((x < 0) && (y < 0)) {
136			    diff = diff + x + x;
137			    x = x + 1;
138			}
139			else {
140			    diff = diff + y + y;
141			    y = y + 1;
142			}
143		    } // else_2_end
144		} // else_1_end
145	    }
146	    else {
147		if ((x >= 0) && (y >= 0)) {
148		    diff = diff + y + y;
149		    y = y + 1;
150		}
151		else { // else_3_begin
152		    if ((x < 0) && (y >= 0)) {
153			diff = diff - x - x;
154			x = x - 1;
155		    }
156		    else { // else_4_begin
157			if ((x < 0) && (y < 0)) {
158			    diff = diff - y - y;
159			    y = y - 1;
160			}
161			else {
162			    diff = x + x;
163			    x = x + 1;
164			}
165		    } // else_4_end
166		} // else_3_end
167	    }
168
169            // send the intermediate x value to port
170
171	    out_sel.write(0);	// Select x
172	    out_wr.write(1);	// Output ready signal
173	    out_xy.write(x);
174	    diffs.write(diff);
175	    wait();
176
177            // handshake x..
178
179	    do { wait(); } while (x_ok == 0);
180	    out_wr.write(0);
181	    wait();
182
183            // send the intermediate y value to port
184
185	    out_sel.write(1);	// Select y
186	    out_wr.write(1);	// Output ready signal
187	    out_xy.write(y);
188	    wait();
189
190            // handshake y..
191
192	    do { wait(); } while (y_ok == 0);
193	    out_wr.write(0);
194	    wait();
195	}  // End of Main_loop
196    }  // End of Reset_loop
197}
198