data_gen.cpp revision 12855:588919e0e4aa
1/***************************************************************************** 2 3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 4 more contributor license agreements. See the NOTICE file distributed 5 with this work for additional information regarding copyright ownership. 6 Accellera licenses this file to you under the Apache License, Version 2.0 7 (the "License"); you may not use this file except in compliance with the 8 License. You may obtain a copy of the License at 9 10 http://www.apache.org/licenses/LICENSE-2.0 11 12 Unless required by applicable law or agreed to in writing, software 13 distributed under the License is distributed on an "AS IS" BASIS, 14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 15 implied. See the License for the specific language governing 16 permissions and limitations under the License. 17 18 *****************************************************************************/ 19 20/***************************************************************************** 21 22 data_gen.cpp -- 23 24 Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 25 26 *****************************************************************************/ 27 28/***************************************************************************** 29 30 MODIFICATION LOG - modifiers, enter your name, affiliation, date and 31 changes you are making here. 32 33 Name, Affiliation, Date: 34 Description of Modification: 35 36 *****************************************************************************/ 37 38#include "common.h" 39#include "add_chain.h" 40 41/******************************************************************************/ 42/*************************** data_gen Function **********************/ 43/******************************************************************************/ 44 45SC_MODULE( DATA_GEN ) 46{ 47 SC_HAS_PROCESS( DATA_GEN ); 48 49 sc_in_clk clk; 50 51 /*** Input and Output Ports ***/ 52 const sc_signal<bool>& ready; 53 signal_bool_vector8& data; 54 sc_signal<int>& addr; 55 56 /*** Constructor ***/ 57 DATA_GEN ( sc_module_name NAME, 58 sc_clock& TICK_N, 59 const sc_signal<bool>& READY, 60 signal_bool_vector8& DATA, 61 sc_signal<int>& ADDR ) 62 63 : 64 ready (READY), 65 data (DATA), // 8 bits 66 addr (ADDR) 67 68 { 69 clk (TICK_N); 70 SC_CTHREAD( entry, clk.neg() ); 71 } 72 73 /*** Call to Process Functionality ***/ 74 void entry(); 75 76}; 77 78void 79DATA_GEN::entry() 80{ 81 while(true) { 82 83/** WAIT FOR POSEDGE OF ready **/ 84 85 do { wait(); } while (ready == 1); // Posedge ready 86 do { wait(); } while (ready == 0); 87 88/** CHECK TO SEE IF THE END OF MEMORY HAS BEEN REACHED **/ 89 90 if(addr.read() > LIMIT) { // if(addr > LIMIT) 91 break; 92 } 93 94/** WRITE VALUE OF MEMORY AT CURRENT ADDRESS TO data **/ 95 96 data.write(mem[addr.read()]); // data = mem[addr] 97 98/** INCREMENT addr BY 1 **/ 99 100 addr.write(addr.read() + 1); // addr = addr + 1 101 } 102 103} 104 105void 106f_DATA_GEN ( const char* NAME, 107 sc_clock& TICK, 108 const sc_signal<bool>& READY, 109 signal_bool_vector8& DATA, 110 sc_signal<int>& ADDR ) 111 112{ 113 new DATA_GEN(NAME, TICK, READY, DATA, ADDR); 114} 115 116