tb.h revision 12855:588919e0e4aa
1/***************************************************************************** 2 3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 4 more contributor license agreements. See the NOTICE file distributed 5 with this work for additional information regarding copyright ownership. 6 Accellera licenses this file to you under the Apache License, Version 2.0 7 (the "License"); you may not use this file except in compliance with the 8 License. You may obtain a copy of the License at 9 10 http://www.apache.org/licenses/LICENSE-2.0 11 12 Unless required by applicable law or agreed to in writing, software 13 distributed under the License is distributed on an "AS IS" BASIS, 14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 15 implied. See the License for the specific language governing 16 permissions and limitations under the License. 17 18 *****************************************************************************/ 19 20/***************************************************************************** 21 22 tb.h -- 23 24 Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 25 26 *****************************************************************************/ 27 28/***************************************************************************** 29 30 MODIFICATION LOG - modifiers, enter your name, affiliation, date and 31 changes you are making here. 32 33 Name, Affiliation, Date: 34 Description of Modification: 35 36 *****************************************************************************/ 37 38/******************************************************************************/ 39/*************************** Testbench Function **********************/ 40/******************************************************************************/ 41/* */ 42/* The testbench module has the following hierarchy: */ 43/* */ 44/* testbench */ 45/* - RESET_STIM */ 46/* - DATA_GEN */ 47/* */ 48/******************************************************************************/ 49 50struct testbench : public sc_module { 51 sc_signal<int> addr; // Address of input memory 52 sc_signal<bool> reset; 53 sc_signal<bool> ready; 54 signal_bool_vector8 data; 55 signal_bool_vector4 sum; 56 RESET_STIM rd1; 57 DATA_GEN dg1; 58 ADD_CHAIN ac1; 59 DISPLAY d1; 60 61 /*** Constructor ***/ 62 testbench ( const sc_module_name& NAME, 63 sc_clock& TICK ) 64 65 : sc_module(), 66 rd1 ("RD1", TICK, ready, reset, addr), 67 dg1 ("DG1", TICK, ready, data, addr), 68 ac1 ("AC1", TICK, reset, data, sum, ready), 69 d1 ("D1", ready, data, sum) 70 71 { 72 end_module(); 73 } 74}; 75