main.cpp revision 12855:588919e0e4aa 
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20/*****************************************************************************
21
22  main.cpp --
23
24  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25
26 *****************************************************************************/
27
28/*****************************************************************************
29
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
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33      Name, Affiliation, Date:
34  Description of Modification:
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36 *****************************************************************************/
37
38//***************************************************************************
39// FILE: main.cc
40//
41// AUTHOR: Luc Semeria    September, 21, 1998
42//
43// ABSTRACT: main (instanciates dw8051 cycle-accurate model and
44//           and peripheral on memory bus
45//
46// MODIFICATION HISTORY:
47//         Luc Semeria: 9/21/98 created
48//
49//***************************************************************************
50//
51// DESCRIPTION
52//
53//   This program tests the communication between the cycle-accurate model
54//   and the peripheral on the memory bus
55//
56//   The peripheral copies the input after a given number of clocks
57//
58//   Reference: Synopsys DesignWare DW8051 MacroCell Databook
59//
60//***************************************************************************
61#include "cycle_model.h"
62#include "peripheral.h"
63// #define DEBUG
64char *hex_file_name;
65
66
67void usage() {
68  fprintf(stdout,"\nusage: hw_sim.x [-a] filename.hex\n");
69  exit(-1);
70}
71
72void parse_arg(int argc, char *argv[]) {
73  extern bool ALL_CYCLES;
74  int i = 1;
75
76  ALL_CYCLES = 0;
77
78#if 0
79  // parse -a
80  if(argc<=i)
81    usage();
82
83  if(!strcmp(argv[i],"-a")) {
84    ALL_CYCLES = 1;
85    i++;
86  }
87
88  // parse file name
89  if(argc<=i)
90    usage();
91
92  hex_file_name=(char *)malloc(strlen(argv[i])*sizeof(char));
93  strcpy(hex_file_name,argv[i]);
94  i++;
95
96  // no more param
97  if(i<argc)
98    usage();
99#else
100  hex_file_name = (char*)malloc(50*sizeof(char));
101  strcpy(hex_file_name,"cycle_dw8051_demo/test.hex");
102#endif
103  return;
104}
105
106//-------------------------------------------------------------------------
107// int sc_main(int argc, char **argv)
108//
109//-------------------------------------------------------------------------
110int sc_main(int argc, char *argv[])
111{
112  // clock -------------------------------------------------------------------
113  sc_clock             clock  ("CLOCK", 40, SC_NS, 0.5); // assume 25MHz
114
115    // signals for read/write to External RAM/ROM
116  signal_bool_vector16    mem_addr("mem_addr");          // address bus
117  signal_bool_vector8     mem_data_out("mem_data_out");  // data out bus
118  signal_bool_vector8     mem_data_in("mem_data_in");    // data in bus
119  sc_signal<bool>         mem_wr_n("mem_wr_n");          // write strobe
120  sc_signal<bool>         mem_rd_n("mem_rd_n");          // read enable sampled
121  sc_signal<bool>         mem_pswr_n("mem_pswr_n");      // write enable (ROM)
122  sc_signal<bool>         mem_psrd_n("mem_psrd_n");      // read enable (ROM)
123  sc_signal<bool>         mem_ale("mem_ale");            // ext latch enable
124  sc_signal<bool>         mem_ea_n("mem_ea_n");          // ext prog mem enable
125
126  // sc_signal<bool>      port_pin_reg_n(); // select read from ext reg or pin
127  sc_signal<bool>         p0_mem_reg_n("p0_mem_reg_n");  // select port reg
128  sc_signal<bool>         p0_addr_data_n("p0_addr_data_n");// select data
129  sc_signal<bool>         p2_mem_reg_n("p2_mem_reg_n");  // cf p0_mem_reg_n
130
131  parse_arg(argc, argv);
132
133  cycle_model CYCLE_MODEL("dw8051",
134			  clock,
135			  hex_file_name,        // name of the hex file
136
137			  mem_addr,
138			  mem_data_out,
139			  mem_data_in,
140			  mem_wr_n,
141			  mem_rd_n,
142			  mem_pswr_n,
143			  mem_psrd_n,
144			  mem_ale,
145			  mem_ea_n,
146
147			  // port_pin_reg_n,
148			  p0_mem_reg_n,
149			  p0_addr_data_n,
150			  p2_mem_reg_n);
151
152  peripheral PERIPHERAL("peripheral",
153		       clock,
154		       mem_addr,
155		       mem_data_out,
156		       mem_data_in,
157		       mem_wr_n,
158                       mem_rd_n,
159                       mem_pswr_n,
160                       mem_psrd_n,
161                       mem_ale,
162                       mem_ea_n,
163
164                       p0_mem_reg_n,
165                       p0_addr_data_n,
166                       p2_mem_reg_n);
167
168
169
170  sc_start();
171  return 0;
172}
173