cycle_model.h revision 12855:588919e0e4aa
1/***************************************************************************** 2 3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 4 more contributor license agreements. See the NOTICE file distributed 5 with this work for additional information regarding copyright ownership. 6 Accellera licenses this file to you under the Apache License, Version 2.0 7 (the "License"); you may not use this file except in compliance with the 8 License. You may obtain a copy of the License at 9 10 http://www.apache.org/licenses/LICENSE-2.0 11 12 Unless required by applicable law or agreed to in writing, software 13 distributed under the License is distributed on an "AS IS" BASIS, 14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 15 implied. See the License for the specific language governing 16 permissions and limitations under the License. 17 18 *****************************************************************************/ 19 20/***************************************************************************** 21 22 cycle_model.h -- 23 24 Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 25 26 *****************************************************************************/ 27 28/***************************************************************************** 29 30 MODIFICATION LOG - modifiers, enter your name, affiliation, date and 31 changes you are making here. 32 33 Name, Affiliation, Date: 34 Description of Modification: 35 36 *****************************************************************************/ 37 38#include "common.h" 39 40#define MEM_SIZE 65536 41#define INT_SIZE 2048 42 43/* types of operands */ 44enum op_type { 45 o_null, 46 o_acc, // accumulator 47 o_reg, // registers Ri 48 o_dir, // internal register direct 49 o_ind, // internal register pointed to by R0 or R1 50 o_ext, // external memory pointed to by R0 or R1 51 o_rel, // 2complement offset byte 52 o_cst, // 8bit constant 53 o_lcst, // 16bit constant 54 o_add, // 11bit destination address 55 o_ladd // 16bit destination address 56}; 57 58 59/* limited set of instruction types */ 60enum instr_type { 61 // arithmetic operations 62 i_add, // 0 63 i_sub, // 1 64 i_inc, // 2 65 i_dec, // 3 66 i_mul, // 4 67 i_div, // 5 68 // logic operations 69 i_and, // 6 70 i_or, // 7 71 i_xor, // 8 72 i_clr, // 9 73 i_cpl, // 10 74 i_rl, // 11 75 i_rr, // 12 76 // data transfer 77 i_mov, // 13 78 // branching 79 i_call,// 14 80 i_ret, // 15 81 i_jmp, // 16 82 i_sjmp,// 17 83 i_jz, // 18 84 i_jnz, // 19 85 i_cjne,// 20 86 i_djnz,// 21 87 i_nop // 22 88}; 89 90 91/* cycle types for memory bus */ 92enum bus_cycle_type { 93 OP_IDLE, 94 OP_MEM_READ, 95 OP_MEM_WRITE 96}; 97 98 99/* ------------------------------------------------------------------------ 100 * struct operand 101 * ----------------------------------------------------------------------*/ 102struct operand { 103 op_type type; 104 int val; /* value encoded with the opcode (i.e. register number) */ 105}; 106 107 108/* ------------------------------------------------------------------------ 109 * struct instr ( instruction ) 110 * ----------------------------------------------------------------------*/ 111struct instr { 112 instr_type type; 113 int n_src; /* number of source operands */ 114 operand src1; /* source operand 1 */ 115 operand src2; /* source operand 2 */ 116 operand dst; /* destination operand */ 117 int cycle; // number of cycles 118}; 119 120 121/* ------------------------------------------------------------------------ 122 * struct stack_el ( stack element ) 123 * ----------------------------------------------------------------------*/ 124struct stack_el { 125 int address; 126 stack_el *up; 127}; 128 129 130 131/* ------------------------------------------------------------------------ 132 * struct cycle_model: public sc_aproc 133 * 134 * ----------------------------------------------------------------------*/ 135 136SC_MODULE( cycle_model ) 137{ 138 SC_HAS_PROCESS( cycle_model ); 139 140 sc_in_clk clk; 141 142 /* functions */ 143 void init(); 144 void parse_hex(char *name); 145 void exec_bus_cycle(bus_cycle_type op, int addr, int data, int* result); 146 bool request_address(int addr); 147 int fetch_instr(int ad); 148 int fetch_data(int ad); 149 int write_data(int ad, int data); 150 int fetch_operand(operand* op); 151 int write_back(operand *, int); 152 void execute(instr *i); 153 void decode(int opcode, instr* i); 154 155 156 /* memory bus */ 157 signal_bool_vector16& mem_addr; 158 signal_bool_vector8& mem_data_out; 159 const signal_bool_vector8& mem_data_in; 160 sc_signal<bool>& mem_wr_n; 161 sc_signal<bool>& mem_rd_n; 162 sc_signal<bool>& mem_pswr_n; 163 sc_signal<bool>& mem_psrd_n; 164 sc_signal<bool>& mem_ale; 165 const sc_signal<bool>& mem_ea_n; 166 167 sc_signal<bool>& p0_mem_reg_n; 168 sc_signal<bool>& p0_addr_data_n; 169 sc_signal<bool>& p2_mem_reg_n; 170 171 /* internal variables */ 172 /* memories registers and stack */ 173 int instr_mem[MEM_SIZE]; /* instruction memory */ 174 int ext_mem[MEM_SIZE]; /* 'external' data memory */ 175 int int_mem[INT_SIZE]; /* internal data memory */ 176 int A; /* accumulator */ 177 int R[8]; /* registers */ 178 stack_el *my_stack; /* stack */ 179 /* others */ 180 int cycles2execute; /* number of cycles to execute */ 181 int cycle_count; /* total number of cycles executed */ 182 int stretch_cycles; /* memory stretch cycles */ 183 184 185 186 /* Constructor */ 187 cycle_model(sc_module_name NAME, 188 const sc_signal_in_if<bool>& CLK, 189 char* hex_file_name, 190 191 signal_bool_vector16& MEM_ADDR, 192 signal_bool_vector8& MEM_DATA_OUT, 193 const signal_bool_vector8& MEM_DATA_IN, 194 sc_signal<bool>& MEM_WR_N, 195 sc_signal<bool>& MEM_RD_N, 196 sc_signal<bool>& MEM_PSWR_N, 197 sc_signal<bool>& MEM_PSRD_N, 198 sc_signal<bool>& MEM_ALE, 199 const sc_signal<bool>& MEM_EA_N, 200 201 sc_signal<bool>& P0_MEM_REG_N, 202 sc_signal<bool>& P0_ADDR_DATA_N, 203 sc_signal<bool>& P2_MEM_REG_N 204 ) 205 : 206 207 mem_addr(MEM_ADDR), 208 mem_data_out(MEM_DATA_OUT), 209 mem_data_in(MEM_DATA_IN), 210 mem_wr_n(MEM_WR_N), 211 mem_rd_n(MEM_RD_N), 212 mem_pswr_n(MEM_PSWR_N), 213 mem_psrd_n(MEM_PSRD_N), 214 mem_ale(MEM_ALE), 215 mem_ea_n(MEM_EA_N), 216 p0_mem_reg_n(P0_MEM_REG_N), 217 p0_addr_data_n(P0_ADDR_DATA_N), 218 p2_mem_reg_n(P2_MEM_REG_N) 219 { 220 clk(CLK); 221 SC_THREAD( entry ); 222 sensitive << clk; 223 224 parse_hex(hex_file_name); 225 init(); 226 } 227 228 /* Process functionality in member function below */ 229 void entry(); 230}; 231