async_clock.cpp revision 12855:588919e0e4aa
1/***************************************************************************** 2 3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 4 more contributor license agreements. See the NOTICE file distributed 5 with this work for additional information regarding copyright ownership. 6 Accellera licenses this file to you under the Apache License, Version 2.0 7 (the "License"); you may not use this file except in compliance with the 8 License. You may obtain a copy of the License at 9 10 http://www.apache.org/licenses/LICENSE-2.0 11 12 Unless required by applicable law or agreed to in writing, software 13 distributed under the License is distributed on an "AS IS" BASIS, 14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 15 implied. See the License for the specific language governing 16 permissions and limitations under the License. 17 18 *****************************************************************************/ 19 20/***************************************************************************** 21 22 async_clock.cpp -- 23 24 Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 25 26 *****************************************************************************/ 27 28/***************************************************************************** 29 30 MODIFICATION LOG - modifiers, enter your name, affiliation, date and 31 changes you are making here. 32 33 Name, Affiliation, Date: 34 Description of Modification: 35 36 *****************************************************************************/ 37 38#include "systemc.h" 39 40SC_MODULE( proc1 ) 41{ 42 SC_HAS_PROCESS( proc1 ); 43 44 sc_in_clk clk; 45 46 proc1( sc_module_name NAME, 47 sc_signal_in_if<bool>& CLK ) 48 { 49 clk( CLK ); 50 SC_CTHREAD( entry, clk.pos() ); 51 } 52 53 void entry() 54 { 55 while (true) { 56 wait(); 57 cout << "Process 1 triggered" << endl; 58 } 59 } 60}; 61 62SC_MODULE( proc2 ) 63{ 64 SC_HAS_PROCESS( proc2 ); 65 66 sc_in_clk clk; 67 68 proc2( sc_module_name NAME, 69 sc_signal_in_if<bool>& CLK ) 70 { 71 clk( CLK ); 72 SC_CTHREAD( entry, clk.pos() ); 73 } 74 75 void entry() 76 { 77 while (true) { 78 wait(); 79 cout << "Process 2 triggered" << endl; 80 } 81 } 82}; 83 84SC_MODULE( proc3 ) 85{ 86 SC_HAS_PROCESS( proc3 ); 87 88 sc_in_clk clk; 89 90 proc3( sc_module_name NAME, 91 sc_signal_in_if<bool>& CLK ) 92 { 93 clk( CLK ); 94 SC_CTHREAD( entry, clk.pos() ); 95 } 96 97 void entry() 98 { 99 while (true) { 100 wait(); 101 cout << "Process 3 triggered" << endl; 102 } 103 } 104}; 105 106 107SC_MODULE( proc4 ) 108{ 109 SC_HAS_PROCESS( proc4 ); 110 111 sc_in<bool> a; 112 sc_in<bool> b; 113 sc_in_clk clk; 114 sc_out_clk c; 115 sc_out_clk d; 116 117 proc4( sc_module_name NAME, 118 sc_signal<bool>& A, 119 sc_signal<bool>& B, 120 sc_signal_in_if<bool>& CLK, 121 sc_signal_out_if<bool>& C, 122 sc_signal_out_if<bool>& D ) 123 { 124 a(A); 125 b(B); 126 clk(CLK); 127 c(C); 128 d(D); 129 SC_METHOD( entry ); 130 sensitive << a << b << clk; 131 } 132 133 void entry() 134 { 135 if ((bool) a == 1) 136 c = clk; 137 else 138 c = 0; 139 140 d = clk & b; 141 } 142}; 143 144#define NS * 1e-9 145 146int 147sc_main( int argc, char* argv[] ) 148{ 149 sc_signal<bool> clk1("clk1"); 150 sc_signal<bool> dclk1("Dclock1"); // First derived clock 151 sc_signal<bool> dclk2("Dclock2"); // Second derived clock 152 153 sc_signal<bool> p("p"), q("q"); 154 155 proc1 p1("p1", clk1); 156 proc2 p2("p2", dclk1); 157 proc3 p3("p3", dclk2); 158 proc4 p4("p4", p, q, clk1, dclk1, dclk2 ); 159 160 sc_start(0, SC_NS); 161 p = 1; 162 q = 1; 163 for (double t = 0; t < 5 NS; t += 1 NS) { 164 clk1 = 1; 165 sc_start( 1, SC_NS ); 166 clk1 = 0; 167 sc_start( 1, SC_NS ); 168 cout << " ***" << endl; 169 } 170 q = 0; 171 for (double t = 0; t < 5 NS; t += 1 NS) { 172 clk1 = 1; 173 sc_start( 1, SC_NS ); 174 clk1 = 0; 175 sc_start( 1, SC_NS ); 176 cout << " ***" << endl; 177 } 178 p = 0; 179 for (double t = 0; t < 5 NS; t += 1 NS) { 180 clk1 = 1; 181 sc_start( 1, SC_NS ); 182 clk1 = 0; 183 sc_start( 1, SC_NS ); 184 cout << " ***" << endl; 185 } 186 187 return 0; 188} 189