test.h revision 12855:588919e0e4aa 
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10    http://www.apache.org/licenses/LICENSE-2.0
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19
20/*****************************************************************************
21
22  test.h --
23
24  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25
26 *****************************************************************************/
27
28/*****************************************************************************
29
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
32
33      Name, Affiliation, Date:
34  Description of Modification:
35
36 *****************************************************************************/
37
38/* Common interface file for test cases
39   Author: PRP
40   */
41
42#include "systemc.h"
43
44SC_MODULE( test )
45{
46        SC_HAS_PROCESS( test );
47
48        sc_in_clk clk;
49
50        // Input Reset Port
51        const sc_signal<bool>& reset_sig;
52
53        // Input Data Ports
54	// const sc_signal<int>& i1;
55	// const sc_signal<int>& i2;
56	// const sc_signal<int>& i3;
57	// const sc_signal<int>& i4;
58	// const sc_signal<int>& i5;
59	sc_in<int> i1;
60	sc_in<int> i2;
61	sc_in<int> i3;
62	sc_in<int> i4;
63	sc_in<int> i5;
64
65        // Input Control Ports
66	const sc_signal<bool>& cont1;
67	const sc_signal<bool>& cont2;
68	const sc_signal<bool>& cont3;
69
70        // Output Data Ports
71	sc_signal<int>& o1;
72	sc_signal<int>& o2;
73	sc_signal<int>& o3;
74	sc_signal<int>& o4;
75	sc_signal<int>& o5;
76
77	// Constructor
78	test (
79        sc_module_name NAME,
80	sc_clock& CLK,
81
82        const sc_signal<bool>& RESET_SIG,
83
84	const sc_signal<int>& I1,
85	const sc_signal<int>& I2,
86	const sc_signal<int>& I3,
87	const sc_signal<int>& I4,
88	const sc_signal<int>& I5,
89
90	const sc_signal<bool>& CONT1,
91	const sc_signal<bool>& CONT2,
92	const sc_signal<bool>& CONT3,
93
94	sc_signal<int>& O1,
95	sc_signal<int>& O2,
96	sc_signal<int>& O3,
97	sc_signal<int>& O4,
98	sc_signal<int>& O5)
99	  : reset_sig(RESET_SIG),
100	  cont1 (CONT1), cont2 (CONT2),
101	    cont3 (CONT3), o1(O1),  o2(O2),  o3(O3),  o4(O4),  o5(O5)
102        {
103          clk(CLK);
104	  i1(I1);  i2(I2);  i3(I3);  i4(I4); i5(I5);
105	  SC_CTHREAD( entry, clk.pos() );
106	  reset_signal_is(reset_sig,true);
107	}
108
109  void entry();
110};
111