pr-503.cpp revision 12855:588919e0e4aa
1/***************************************************************************** 2 3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 4 more contributor license agreements. See the NOTICE file distributed 5 with this work for additional information regarding copyright ownership. 6 Accellera licenses this file to you under the Apache License, Version 2.0 7 (the "License"); you may not use this file except in compliance with the 8 License. You may obtain a copy of the License at 9 10 http://www.apache.org/licenses/LICENSE-2.0 11 12 Unless required by applicable law or agreed to in writing, software 13 distributed under the License is distributed on an "AS IS" BASIS, 14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 15 implied. See the License for the specific language governing 16 permissions and limitations under the License. 17 18 *****************************************************************************/ 19 20/***************************************************************************** 21 22 pr-503.cpp -- 23 24 Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 25 26 *****************************************************************************/ 27 28/***************************************************************************** 29 30 MODIFICATION LOG - modifiers, enter your name, affiliation, date and 31 changes you are making here. 32 33 Name, Affiliation, Date: 34 Description of Modification: 35 36 *****************************************************************************/ 37 38#include "systemc.h" 39 40struct EXC_CTRL : sc_module { 41 42 // Input ports 43 sc_in<bool> RPHB_RESET; 44 sc_in<bool> RPHB_REG_RST; 45 sc_in<bool> IBC_GRANT_EXC; 46 sc_in<sc_int<16> > IBC_DATA; 47 sc_in<sc_int<4> > RPBI_BPA; 48 sc_in<sc_int<2> > RPBI_APA; 49 sc_in<bool> MODE_S_P; 50 sc_in<sc_int<14> > RHC_ADDR_RT; 51 sc_in<bool> RHC_OP_END; 52 sc_in<bool> RHC_REG_RST; 53 sc_in<sc_int<4> > TM_EXC_FIR; 54 55 // clock port 56 sc_in_clk RHC_RPHB_CLK; 57 58 // Output ports 59 sc_out<bool> EXC_REQ; 60 sc_out<sc_int<14> > EXC_ADDR; 61 sc_out<sc_int<16> > EXC_DATA; 62 sc_out<bool> EXC_RW; 63 sc_out<bool> EXC_IDLE0; 64 sc_out<bool> EXC_IDLE1; 65 sc_out<sc_int<2> > EXC_RPBH_ID; 66 sc_out<sc_int<3> > RHC_OP_CODE; 67 sc_out<bool> RHC_OP_START; 68 sc_out<sc_int<7> > RHC_SIZE; 69 sc_out<sc_int<14> > RHC_ADDR1; 70 sc_out<sc_int<14> > RHC_ADDR2; 71 sc_out<sc_int<3> > EXC_ERR_NO; 72 73 SC_HAS_PROCESS( EXC_CTRL ); 74 75 EXC_CTRL(char *name) : sc_module(name) { 76 SC_CTHREAD( start_always, RHC_RPHB_CLK.pos() ); 77 // reset 78 reset_signal_is(RPHB_RESET,true); 79 end_module(); 80 }; 81 void start_always(); 82}; 83void EXC_CTRL::start_always() { 84 sc_int<16> dt; 85 sc_int<16> dtemp; 86 sc_int<8> dtemp_1; 87 sc_int<14> atemp; 88 sc_int<14> atemp_1; 89 sc_int<14> atemp_2; 90 sc_int<14> atemp_3; 91 sc_int<14> atemp_4; 92 sc_int<8> timer; 93 bool V_reg; 94 sc_int<5> DID_reg; 95 sc_int<5> MET_reg; 96 sc_int<6> Data_Start_reg; 97 sc_int<12> total_data_len; 98 sc_int<7> link_ptr; 99 sc_int<7> index; 100 sc_int<2> LEV_reg; 101 sc_int<4> DT_reg; 102 sc_int<6> NHW_reg; 103 sc_int<8> RSN_reg; 104 sc_int<8> RP_addr_ptr; 105 sc_int<12> cnt; 106 sc_int<7> sig_gen_buff_addr; 107 sc_int<5> TS0AR; 108 sc_int<5> TS1AR; 109 bool GB_1_ind; 110 bool GB_ext_flg; 111 sc_int<2> id_reg; 112 sc_int<3> err_no_reg; 113 bool rb_flag; 114 sc_int<32> _case_1021_; 115 sc_int<32> _case_1396_; 116 sc_int<16> _case_1934_; 117 sc_int<16> _case_2503_; 118 119 sc_int<3> error; 120 start: while(1) { 121 122 // reset action 123 reset_action: 124 { 125 dt = 0; 126 dtemp_1 = 0; 127 atemp = 0; 128 atemp_1 = 0; 129 atemp_2 = 0; 130 atemp_3 = 0; 131 atemp_4 = 0; 132 timer = 0; 133 V_reg = 0; 134 DID_reg = 0; 135 MET_reg = 0; 136 Data_Start_reg = 0; 137 total_data_len = 0; 138 link_ptr = 0; 139 index = 0; 140 LEV_reg = 0; 141 DT_reg = 0; 142 NHW_reg = 0; 143 RSN_reg = 0; 144 RP_addr_ptr = 0; 145 cnt = 0; 146 sig_gen_buff_addr = 0; 147 TS0AR = 0; 148 TS1AR = 0; 149 GB_1_ind = 0; 150 GB_ext_flg = 0; 151 id_reg = -1; 152 err_no_reg = 0; 153 rb_flag = 0; 154 EXC_IDLE0 = 1; 155 EXC_IDLE1 = 1; 156 error = 0; 157 EXC_REQ = 0; 158 RHC_OP_START = 0; 159 } 160 wait(); 161 162 163 // continue with the normal operation 164 165 if(RPHB_REG_RST.read()==1) { // init_reg_op 166 // Initialise programmable register#10, #8, #4, #9, #7, #5 and #6 for hard reset 167 // Reset STATISTIC_0 register(register #10) 168 // `write_mem 169 dt = 0; 170 atemp = 0; 171 EXC_ADDR = atemp; 172 EXC_DATA = dt; 173 EXC_RW = 0; 174 EXC_REQ = 1; 175 wait(); 176 while(1) { //wr_01 177 EXC_REQ = 0; 178 if(IBC_GRANT_EXC.read()==1) { 179 wait(); 180 break; 181 } 182 wait(); 183 } //wr_01 184 185 // Reset STATISTIC_1 register(register #10) 186 // 'write_mem 187 atemp = 1; 188 EXC_ADDR = atemp; 189 EXC_DATA = dt; 190 EXC_RW = 0; 191 EXC_REQ = 1; 192 wait(); 193 while(1) { //wr_02 194 EXC_REQ = 0; 195 if(IBC_GRANT_EXC.read()==1) { 196 wait(); 197 break; 198 } 199 wait(); 200 } //wr_02 201 202 // Initialize SSADR_0/POLL_0 register(register #8) 203 if(MODE_S_P.read()==1) { 204 dt = 0; 205 } else { 206 dt = 16; 207 } 208 209 // 'write_mem 210 atemp = 2; 211 EXC_ADDR = atemp; 212 EXC_DATA = dt; 213 EXC_RW = 0; 214 EXC_REQ = 1; 215 wait(); 216 while(1) { // wr_03 217 EXC_REQ = 0; 218 if(IBC_GRANT_EXC.read()==1) { 219 wait(); 220 break; 221 } 222 wait(); 223 } // wr_03 224 225 // Initialize SSADR_1/POLL_1 register(register #8) 226 // 'write_mem 227 atemp = 4; 228 EXC_ADDR = atemp; 229 EXC_DATA = dt; 230 EXC_RW = 0; 231 EXC_REQ = 1; 232 wait(); 233 while(1) { //wr_04 234 EXC_REQ = 0; 235 if(IBC_GRANT_EXC.read()==1) { 236 wait(); 237 break; 238 } 239 wait(); 240 } //wr_04 241 242 // Reset RPHB_0 registers(register #4) 243 RHC_ADDR1 = 8; 244 RHC_ADDR2 = 0; 245 RHC_SIZE = 2; 246 247 // (begin)MACRO: 'set_mem 248 RHC_OP_CODE = 2; 249 RHC_OP_START = 1; 250 wait(); 251 while(!RHC_OP_END.read()) { 252 wait(); 253 continue; 254 } 255 wait(); 256 RHC_OP_START = 0; 257 wait(); 258 // (end)MACRO: 'set_mem 259 260 EXC_ADDR = 10; 261 EXC_DATA = 100; 262 EXC_RW = 0; 263 EXC_REQ = 1; 264 wait(); 265 266 while(1) { // wr_idle_delay_timer_0 267 EXC_REQ = 0; 268 if(IBC_GRANT_EXC.read()==1) { 269 wait(); 270 break; 271 } 272 wait(); 273 }// wr_idle_delay_timer_0 274 275 // Reset RPHB_1 registers(register #4) 276 RHC_ADDR1 = 16; 277 278 // (begin)MACRO: 'set_mem 279 RHC_OP_CODE = 2; 280 RHC_OP_START = 1; 281 wait(); 282 while(!RHC_OP_END.read()) { 283 wait(); 284 continue; 285 } 286 wait(); 287 RHC_OP_START = 0; 288 wait(); 289 // (end)MACRO: 'set_mem 290 291 // Initialize NOT_IDLE_TIMER register for RPBH1 292 EXC_ADDR = 18; 293 EXC_DATA = 100; 294 EXC_RW = 0; 295 EXC_REQ = 1; 296 wait(); 297 while(1) {// wr_idle_delay_timer_1 298 EXC_REQ = 0; 299 if(IBC_GRANT_EXC.read()==1) { 300 wait(); 301 break; 302 } 303 wait(); 304 }// wr_idle_delay_timer_1 305 306 // Set default value to RHC_PEQ registers(register #9) 307 RHC_ADDR1 = 20; 308 RHC_ADDR2 = 50; 309 RHC_SIZE = 4; 310 311 // (begin)MACRO: 'set_mem 312 RHC_OP_CODE = 2; 313 RHC_OP_START = 1; 314 wait(); 315 while(!RHC_OP_END.read()) { 316 wait(); 317 continue; 318 } 319 wait(); 320 RHC_OP_START = 0; 321 wait(); 322 // (end)MACRO: 'set_mem 323 324 // Reset RPB_P/RPB_S registers(register #7) 325 if(!MODE_S_P.read()==1) { 326 atemp = 37; 327 atemp_1 = 53; 328 RHC_SIZE = 5; 329 } else { 330 atemp = 35; 331 atemp_1 = 51; 332 RHC_SIZE = 3; 333 } 334 335 RHC_ADDR2 = 0; 336 RHC_ADDR1 = 32; 337 338 // (begin)MACRO: 'set_mem 339 RHC_OP_CODE = 2; 340 RHC_OP_START = 1; 341 wait(); 342 while(!RHC_OP_END.read()) { 343 wait(); 344 continue; 345 } 346 wait(); 347 RHC_OP_START = 0; 348 wait(); 349 // (end)MACRO: 'set_mem 350 351 dt = 30; 352 EXC_ADDR = atemp; 353 EXC_DATA = dt; 354 EXC_RW = 0; 355 EXC_REQ = 1; 356 wait(); 357 while(1) {// wr_05 358 EXC_REQ = 0; 359 if(IBC_GRANT_EXC.read()==1) { 360 wait(); 361 break; 362 } 363 wait(); 364 }// wr_05 365 366 RHC_ADDR1 = 48; 367 368 // (begin)MACRO: 'set_mem 369 RHC_OP_CODE = 2; 370 RHC_OP_START = 1; 371 wait(); 372 while(!RHC_OP_END.read()) { 373 wait(); 374 continue; 375 } 376 wait(); 377 RHC_OP_START = 0; 378 wait(); 379 // (end)MACRO: 'set_mem 380 381 atemp = atemp_1; 382 EXC_ADDR = atemp; 383 EXC_DATA = dt; 384 EXC_RW = 0; 385 EXC_REQ = 1; 386 wait(); 387 while(1) {// wr_06 388 EXC_REQ = 0; 389 if(IBC_GRANT_EXC.read()==1) { 390 wait(); 391 break; 392 } 393 wait(); 394 }// wr_06 395 396 // Reset RPBH_0/RPBH_1 RP state table(register #5) 397 RHC_ADDR1 = 64; 398 RHC_ADDR2 = 2; 399 RHC_SIZE = 32; 400 401 // (begin)MACRO: 'set_mem 402 RHC_OP_CODE = 2; 403 RHC_OP_START = 1; 404 wait(); 405 while(!RHC_OP_END.read()) { 406 wait(); 407 continue; 408 } 409 wait(); 410 RHC_OP_START = 0; 411 wait(); 412 // (end)MACRO: 'set_mem 413 414 415 RHC_ADDR1 = 96; 416 417 // (begin)MACRO: 'set_mem 418 RHC_OP_CODE = 2; 419 RHC_OP_START = 1; 420 wait(); 421 while(!RHC_OP_END.read()) { 422 wait(); 423 continue; 424 } 425 wait(); 426 RHC_OP_START = 0; 427 wait(); 428 // (end)MACRO: 'set_mem 429 430 // Reset RPBH_0/RPBH_1 EM list table(register #6) 431 RHC_ADDR1 = 128; 432 RHC_ADDR2 = 0; 433 434 // (begin)MACRO: 'set_mem 435 RHC_OP_CODE = 2; 436 RHC_OP_START = 1; 437 wait(); 438 while(!RHC_OP_END.read()) { 439 wait(); 440 continue; 441 } 442 wait(); 443 RHC_OP_START = 0; 444 wait(); 445 // (end)MACRO: 'set_mem 446 447 RHC_ADDR1 = 160; 448 449 // (begin)MACRO: 'set_mem 450 RHC_OP_CODE = 2; 451 RHC_OP_START = 1; 452 wait(); 453 while(!RHC_OP_END.read()) { 454 wait(); 455 continue; 456 } 457 wait(); 458 RHC_OP_START = 0; 459 wait(); 460 // (end)MACRO: 'set_mem 461 462 } else { 463 wait(); 464 } // init_reg_op 465 466 // Initialise FPP/LPP in all Buffer Queues for both hard and soft reset 467 atemp = 270; 468 dt = 0; 469 470 //buf_empty_loop(begin) 471 buf_empty_op: while(1) { 472 EXC_ADDR = atemp; 473 EXC_DATA = dt; 474 EXC_RW = 0; 475 EXC_REQ = 1; 476 wait(); 477 while(1) {// wr_07 478 EXC_REQ = 0; 479 if(IBC_GRANT_EXC.read()==1) { 480 wait(); 481 break; 482 } 483 wait(); 484 }// wr_07 485 486 atemp = (atemp) + 1; 487 EXC_ADDR = atemp; 488 EXC_DATA = dt; 489 EXC_RW = 0; 490 EXC_REQ = 1; 491 wait(); 492 while(1) {// wr_08 493 EXC_REQ = 0; 494 if(IBC_GRANT_EXC.read()==1) { 495 wait(); 496 break; 497 } 498 wait(); 499 }// wr_08 500 atemp = (atemp) + 15; 501 if((atemp.range(8,4)) >= -4) { 502 wait(); 503 break; 504 } else { 505 wait(); 506 } 507 }//buf_empty_loop(end) 508 509 // Initialise all Generic Buffers for both hard and soft reset 510 atemp = 514; 511 V_reg = 0; 512 link_ptr = 5; 513 dt = (((sc_int<1>(V_reg), sc_int<1>(0)), link_ptr.range(5,0)), sc_int<8>(0)); 514 515 // GB_init_loop(begin) 516 GB_init_op: while(1) { 517 EXC_ADDR = atemp; 518 EXC_DATA = dt; 519 EXC_RW = 0; 520 EXC_REQ = 1; 521 wait(); 522 while(1) { // wr_09 523 EXC_REQ = 0; 524 if(IBC_GRANT_EXC.read()==1) { 525 wait(); 526 break; 527 } 528 wait(); 529 } // wr_09 530 531 atemp = (atemp) + 128; 532 if(((bool)atemp[13]) == 1) { 533 wait(); 534 break; 535 } else { 536 wait(); 537 } 538 539 link_ptr = (link_ptr) + 1; 540 if(((bool)link_ptr[6]) == 1) { 541 link_ptr = 0; 542 } else { 543 link_ptr = link_ptr; 544 } 545 dt = (((sc_int<1>(V_reg), sc_int<1>(0)), link_ptr.range(5,0)), sc_int<8>(0)); 546 } // GB_init_loop(end) 547 548 atemp = -8190; 549 dt = 63; 550 551 EXC_ADDR = atemp; 552 EXC_DATA = dt; 553 EXC_RW = 0; 554 EXC_REQ = 1; 555 wait(); 556 557 while(1) {// wr_09_1 558 EXC_REQ = 0; 559 if(IBC_GRANT_EXC) { 560 wait(); 561 break; 562 } 563 wait(); 564 }// wr_09_1 565 566 wait(); 567 568 // RPHB Signals handling part 569 main: while(1) { 570 wait(); 571 signal_proc: do{ 572 573 // Set RPBH_0/RPBH_1 ID active 574 // Reset internal error number and flag for return buffer 575 id_reg = -1; 576 err_no_reg = 0; 577 rb_flag = 0; 578 //*************************************************************** 579 /* #### Modified 19/2/98 EJH #### 580 PEQ code removed from here. PEQ code now only executed if BQ 581 is empty 582 */ 583 //*************************************************************** 584 wait(); 585 // Read the queue(RPHBport -> ExecCtrl) 586 RHC_ADDR1 = 256; 587 //MACRO:read_queue(begin) 588 RHC_OP_CODE = 0; 589 EXC_RPBH_ID = id_reg; 590 RHC_OP_START = 1; 591 wait(); 592 while(!RHC_OP_END.read()) { 593 wait(); 594 continue; 595 } 596 wait(); 597 RHC_OP_START = 0; 598 dtemp.range(13,0) = RHC_ADDR_RT; 599 wait(); 600 //MACRO:read_queue(end) 601 602 sig_gen_buff_addr = dtemp.range(13,7); 603 604 if((sig_gen_buff_addr.range(6,5)) == -1) { // **** If BQ empty 605 wait(); 606 607 // Show idle state for both channels 608 EXC_IDLE0 = 1; 609 EXC_IDLE1 = 1; 610 611 // Read the queue poll time 612 atemp = 22; 613 EXC_ADDR = atemp; 614 EXC_RPBH_ID = id_reg; 615 EXC_RW = 1; 616 EXC_REQ = 1; 617 wait(); 618 while(1) {// rd_01 619 dtemp = IBC_DATA.read(); 620 EXC_REQ = 0; 621 if(IBC_GRANT_EXC) { 622 wait(); 623 break; 624 } 625 wait(); 626 }// rd_01 627 628 // Set the timer accordingly and wait 629 timer = dtemp.range(7,0); 630 wait(); 631 while(timer) { 632 timer = (timer) - 1; 633 wait(); 634 continue; 635 } 636 continue; 637 } else { // **** BQ contains pointers 638 wait(); 639 } 640 641 // Read the header of Generic Buffer addressed by FPP pointer 642 atemp = (sig_gen_buff_addr, sc_int<7>(0)); 643 644 EXC_ADDR = atemp; 645 EXC_RPBH_ID = id_reg; 646 EXC_RW = 1; 647 EXC_REQ = 1; 648 wait(); 649 while(1) { // rd_02 650 dtemp = IBC_DATA.read(); 651 EXC_REQ = 0; 652 if(IBC_GRANT_EXC) { 653 wait(); 654 break; 655 } 656 wait(); 657 }// rd_02 658 659 // Combine with Fault Insertion bit 660 DID_reg = (dtemp.range(4,0)) | (((TM_EXC_FIR.read())[1], sc_int<4>(0))); 661 MET_reg = dtemp.range(9,5); 662 if((DID_reg) > 2) { 663 err_no_reg = 1; 664 rb_flag = 1; 665 wait(); 666 // Show idle state for both channels 667 EXC_IDLE0 = 1; 668 EXC_IDLE1 = 1; 669 break; //goto _signal_proc__END; 670 } else { 671 err_no_reg = err_no_reg; 672 rb_flag = rb_flag; 673 wait(); 674 } 675 676 // Set the no. for RPBH being handled 677 id_reg = (!(DID_reg[0]), !(DID_reg[1])); 678 679 // Set the idle outputs 680 EXC_IDLE0 = DID_reg[1]; 681 EXC_IDLE1 = DID_reg[0]; 682 683 // Read inf0 from the Signal being handled 684 atemp = (sig_gen_buff_addr, sc_int<7>(8)); 685 EXC_ADDR = atemp; 686 EXC_RPBH_ID = id_reg; 687 EXC_RW = 1; 688 EXC_REQ = 1; 689 wait(); 690 while(1) {// rd_03 691 dtemp = IBC_DATA.read(); 692 EXC_REQ = 0; 693 if(IBC_GRANT_EXC) { 694 wait(); 695 break; 696 } 697 wait(); 698 }// rd_03 699 700 // Combine with Fault Insertion bit 701 if((TM_EXC_FIR.read())[2]) { 702 dtemp = 254; 703 } else { 704 dtemp = dtemp; 705 } 706 wait(); 707 708 _case_1021_ = dtemp.range(7,0); 709 switch((int)_case_1021_) { 710 // if(193 == _case_1021_) { 711 case 193: 712 if(((MET_reg) != 3) || ((DID_reg) != 0)) { 713 err_no_reg = 1; 714 rb_flag = 1; 715 wait(); 716 } else { 717 wait(); 718 id_reg = 1; 719 err_no_reg = err_no_reg; 720 rb_flag = rb_flag; 721 //RHC_ADDR1 = (((sc_int<4>(0), sig_gen_buff_addr), RPBI_BPA.read()), sc_int<1>(MODE_S_P.read())); 722 RHC_ADDR1 = (((sc_int<4>(0), sig_gen_buff_addr), sc_int<4>(RPBI_BPA.read())), sc_int<1>(MODE_S_P.read())); 723 RHC_ADDR2 = ((sc_int<8>(10), TS0AR), sc_int<1>(RHC_REG_RST.read())); 724 RHC_OP_CODE = -4; 725 RHC_OP_START = 1; 726 wait(); 727 while(!RHC_OP_END.read()) { 728 wait(); 729 continue; 730 } 731 wait(); 732 RHC_OP_START = 0; 733 wait(); 734 RHC_ADDR1 = 272; 735 RHC_ADDR2 = (sig_gen_buff_addr, sc_int<7>(0)); 736 RHC_OP_CODE = 1; 737 EXC_RPBH_ID = id_reg; 738 RHC_OP_START = 1; 739 wait(); 740 while(!RHC_OP_END.read()) { 741 wait(); 742 continue; 743 } 744 wait(); 745 RHC_OP_START = 0; 746 wait(); 747 id_reg = -2; 748 EXC_ADDR = -8192; 749 EXC_RPBH_ID = id_reg; 750 EXC_RW = 1; 751 EXC_REQ = 1; 752 wait(); 753 while(1) { 754 dtemp = IBC_DATA.read(); 755 EXC_REQ = 0; 756 if(IBC_GRANT_EXC) { 757 wait(); 758 break; 759 } 760 wait(); 761 } 762 //RHC_ADDR1 = (((sc_int<4>(0), dtemp.range(13,7)), RPBI_BPA.read()), sc_int<1>(MODE_S_P.read())); 763 RHC_ADDR1 = (((sc_int<4>(0), dtemp.range(13,7)), sc_int<4>(RPBI_BPA.read())), sc_int<1>(MODE_S_P.read())); 764 RHC_ADDR2 = ((sc_int<8>(11), TS1AR), sc_int<1>(RHC_REG_RST.read())); 765 RHC_OP_CODE = -4; 766 RHC_OP_START = 1; 767 wait(); 768 while(!RHC_OP_END.read()) { 769 wait(); 770 continue; 771 } 772 wait(); 773 RHC_OP_START = 0; 774 wait(); 775 RHC_ADDR1 = 288; 776 RHC_ADDR2 = (dtemp.range(13,7), sc_int<7>(0)); 777 RHC_OP_CODE = 1; 778 EXC_RPBH_ID = id_reg; 779 RHC_OP_START = 1; 780 wait(); 781 while(!RHC_OP_END.read()) { 782 wait(); 783 continue; 784 } 785 wait(); 786 RHC_OP_START = 0; 787 wait();} 788 break; 789 // } else if(1 == _case_1021_) { 790 case 1: 791 if(((MET_reg) != 3) || ((DID_reg) != 1)) { 792 err_no_reg = 1; 793 rb_flag = 1; 794 wait(); 795 } else { 796 wait(); 797 err_no_reg = err_no_reg; 798 rb_flag = 1; 799 atemp = (sig_gen_buff_addr, sc_int<7>(10)); 800 EXC_ADDR = atemp; 801 EXC_RPBH_ID = id_reg; 802 EXC_RW = 1; 803 EXC_REQ = 1; 804 wait(); 805 while(1) { 806 dtemp = IBC_DATA.read(); 807 EXC_REQ = 0; 808 if(IBC_GRANT_EXC) { 809 wait(); 810 break; 811 } 812 wait(); 813 } 814 TS0AR = dtemp.range(4,0); 815 TS1AR = (TS0AR) + 1; 816 atemp = (sig_gen_buff_addr, sc_int<7>(11)); 817 EXC_ADDR = atemp; 818 EXC_RPBH_ID = id_reg; 819 EXC_RW = 1; 820 EXC_REQ = 1; 821 wait(); 822 while(1) { 823 dtemp = IBC_DATA.read(); 824 EXC_REQ = 0; 825 if(IBC_GRANT_EXC) { 826 wait(); 827 break; 828 } 829 wait(); 830 } 831 dt = dtemp; 832 atemp = 9; 833 EXC_ADDR = atemp; 834 EXC_DATA = dt; 835 EXC_RW = 0; 836 EXC_REQ = 1; 837 wait(); 838 while(1) { 839 EXC_REQ = 0; 840 if(IBC_GRANT_EXC) { 841 wait(); 842 break; 843 } 844 wait(); 845 } 846 dt = (dt) + 32; 847 atemp = 17; 848 EXC_ADDR = atemp; 849 EXC_DATA = dt; 850 EXC_RW = 0; 851 EXC_REQ = 1; 852 wait(); 853 while(1) { 854 EXC_REQ = 0; 855 if(IBC_GRANT_EXC) { 856 wait(); 857 break; 858 } 859 wait(); 860 } 861 } 862 break; 863 // } else if((((194 == _case_1021_) || (201 == _case_1021_)) || (205 == _case_1021_)) || (204 == _case_1021_)) { 864 case 194:; 865 case 201:; 866 case 205:; 867 868 if(((MET_reg) != 3) || ((DID_reg) != 0)) { 869 err_no_reg = 1; 870 rb_flag = 1; 871 wait(); 872 } else { 873 err_no_reg = err_no_reg; 874 rb_flag = 1; 875 wait(); 876 } 877 break; 878 // } else if(209 == _case_1021_) { 879 case 209: 880 if(((MET_reg) != 3) || ((DID_reg) == 0)) { 881 err_no_reg = 1; 882 rb_flag = 1; 883 wait(); 884 } else { 885 err_no_reg = err_no_reg; 886 rb_flag = 1; 887 wait(); 888 } 889 break; 890 //} else if(7 == _case_1021_) { 891 case 7: 892 if(((MET_reg) != 3) || ((DID_reg) == 0)) { 893 err_no_reg = 1; 894 rb_flag = 1; 895 wait(); 896 } else { 897 wait(); 898 err_no_reg = err_no_reg; 899 rb_flag = rb_flag; 900 if((DID_reg[0]) == 1) { 901 DID_reg = 10; 902 atemp_1 = 272; 903 } else { 904 DID_reg = 11; 905 atemp_1 = 288; 906 } 907 RHC_ADDR1 = (sig_gen_buff_addr, sc_int<7>(0)); 908 RHC_ADDR2 = 0; 909 RHC_SIZE = ((sc_int<1>(0), DID_reg), sc_int<1>(0)); 910 RHC_OP_CODE = -3; 911 RHC_OP_START = 1; 912 wait(); 913 while(!RHC_OP_END.read()) { 914 wait(); 915 continue; 916 } 917 wait(); 918 RHC_OP_START = 0; 919 wait(); 920 RHC_ADDR1 = 451; 921 RHC_ADDR2 = 0; 922 RHC_SIZE = sig_gen_buff_addr; 923 RHC_OP_CODE = -2; 924 RHC_OP_START = 1; 925 wait(); 926 while(!RHC_OP_END.read()) { 927 wait(); 928 continue; 929 } 930 wait(); 931 RHC_OP_START = 0; 932 wait(); 933 atemp = (sig_gen_buff_addr, sc_int<7>(11)); 934 dt = 1; 935 EXC_ADDR = atemp; 936 EXC_DATA = dt; 937 EXC_RW = 0; 938 EXC_REQ = 1; 939 wait(); 940 while(1) { 941 EXC_REQ = 0; 942 if(IBC_GRANT_EXC) { 943 wait(); 944 break; 945 } 946 wait(); 947 } 948 atemp = (sig_gen_buff_addr, sc_int<7>(12)); 949 dt = 0; 950 EXC_ADDR = atemp; 951 EXC_DATA = dt; 952 EXC_RW = 0; 953 EXC_REQ = 1; 954 wait(); 955 while(1) { 956 EXC_REQ = 0; 957 if(IBC_GRANT_EXC) { 958 wait(); 959 break; 960 } 961 wait(); 962 } 963 RHC_ADDR1 = atemp_1; 964 RHC_ADDR2 = (sig_gen_buff_addr, sc_int<7>(0)); 965 RHC_OP_CODE = 1; 966 EXC_RPBH_ID = id_reg; 967 RHC_OP_START = 1; 968 wait(); 969 while(!RHC_OP_END.read()) { 970 wait(); 971 continue; 972 } 973 wait(); 974 RHC_OP_START = 0; 975 wait(); 976 } 977 break; 978 // } else if(59 == _case_1021_) { 979 case 59: 980 if(((MET_reg) != 3) || ((DID_reg) == 0)) { 981 err_no_reg = 1; 982 rb_flag = 1; 983 wait(); 984 } else { 985 wait(); 986 err_no_reg = err_no_reg; 987 rb_flag = rb_flag; 988 atemp = (sig_gen_buff_addr, sc_int<7>(10)); 989 EXC_ADDR = atemp; 990 EXC_RPBH_ID = id_reg; 991 EXC_RW = 1; 992 EXC_REQ = 1; 993 wait(); 994 while(1) { 995 dtemp = IBC_DATA.read(); 996 EXC_REQ = 0; 997 if(IBC_GRANT_EXC) { 998 wait(); 999 break; 1000 } 1001 wait(); 1002 } 1003 RP_addr_ptr = dtemp.range(7,0); 1004 if((DID_reg[0]) == 1) { 1005 RP_addr_ptr = (sc_int<3>(2), RP_addr_ptr.range(4,0)); 1006 DID_reg = 10; 1007 atemp_1 = (sc_int<9>(4), RP_addr_ptr.range(4,0)); 1008 atemp_2 = 9; 1009 atemp_3 = 272; 1010 } else { 1011 RP_addr_ptr = (sc_int<3>(3), RP_addr_ptr.range(4,0)); 1012 DID_reg = 11; 1013 atemp_1 = (sc_int<9>(5), RP_addr_ptr.range(4,0)); 1014 atemp_2 = 17; 1015 atemp_3 = 288; 1016 } 1017 atemp = (sig_gen_buff_addr, sc_int<7>(11)); 1018 EXC_ADDR = atemp; 1019 EXC_RPBH_ID = id_reg; 1020 EXC_RW = 1; 1021 EXC_REQ = 1; 1022 wait(); 1023 while(1) { 1024 dtemp = IBC_DATA.read(); 1025 EXC_REQ = 0; 1026 if(IBC_GRANT_EXC) { 1027 wait(); 1028 break; 1029 } 1030 wait(); 1031 } 1032 } 1033 _case_1396_ = int(dtemp); 1034 switch((int)_case_1396_) { 1035 // if(1 == _case_1396_) { 1036 case 1: 1037 rb_flag = 1; 1038 atemp = (sc_int<6>(0), RP_addr_ptr); 1039 EXC_ADDR = atemp; 1040 EXC_RPBH_ID = id_reg; 1041 EXC_RW = 1; 1042 EXC_REQ = 1; 1043 wait(); 1044 while(1) { 1045 dtemp = IBC_DATA.read(); 1046 EXC_REQ = 0; 1047 if(IBC_GRANT_EXC) { 1048 wait(); 1049 break; 1050 } 1051 wait(); 1052 } 1053 dt = dtemp | 2; 1054 EXC_ADDR = atemp; 1055 EXC_DATA = dt; 1056 EXC_RW = 0; 1057 EXC_REQ = 1; 1058 wait(); 1059 while(1) { 1060 EXC_REQ = 0; 1061 if(IBC_GRANT_EXC) { 1062 wait(); 1063 break; 1064 } 1065 wait(); 1066 } 1067 break; 1068 // } else if(2 == _case_1396_) { 1069 case 2: 1070 rb_flag = 1; 1071 atemp = (sc_int<6>(0), RP_addr_ptr); 1072 EXC_ADDR = atemp; 1073 EXC_RPBH_ID = id_reg; 1074 EXC_RW = 1; 1075 EXC_REQ = 1; 1076 wait(); 1077 while(1) { 1078 dtemp = IBC_DATA.read(); 1079 EXC_REQ = 0; 1080 if(IBC_GRANT_EXC) { 1081 wait(); 1082 break; 1083 } 1084 wait(); 1085 } 1086 dt = dtemp & -3; 1087 EXC_ADDR = atemp; 1088 EXC_DATA = dt; 1089 EXC_RW = 0; 1090 EXC_REQ = 1; 1091 wait(); 1092 while(1) { 1093 EXC_REQ = 0; 1094 if(IBC_GRANT_EXC) { 1095 wait(); 1096 break; 1097 } 1098 wait(); 1099 } 1100 break; 1101 // } else if(3 == _case_1396_) { 1102 case 3: 1103 rb_flag = 1; 1104 atemp = (sig_gen_buff_addr, sc_int<7>(12)); 1105 EXC_ADDR = atemp; 1106 EXC_RPBH_ID = id_reg; 1107 EXC_RW = 1; 1108 EXC_REQ = 1; 1109 wait(); 1110 while(1) { 1111 dtemp = IBC_DATA.read(); 1112 EXC_REQ = 0; 1113 if(IBC_GRANT_EXC) { 1114 wait(); 1115 break; 1116 } 1117 wait(); 1118 } 1119 atemp = atemp_1; 1120 dt = dtemp; 1121 EXC_ADDR = atemp; 1122 EXC_DATA = dt; 1123 EXC_RW = 0; 1124 EXC_REQ = 1; 1125 wait(); 1126 while(1) { 1127 EXC_REQ = 0; 1128 if(IBC_GRANT_EXC) { 1129 wait(); 1130 break; 1131 } 1132 wait(); 1133 } break; 1134 // } else if(4 == _case_1396_) { 1135 case 4: 1136 atemp = atemp_2; 1137 EXC_ADDR = atemp; 1138 EXC_RPBH_ID = id_reg; 1139 EXC_RW = 1; 1140 EXC_REQ = 1; 1141 wait(); 1142 while(1) { 1143 dtemp = IBC_DATA.read(); 1144 EXC_REQ = 0; 1145 if(IBC_GRANT_EXC) { 1146 wait(); 1147 break; 1148 } 1149 wait(); 1150 } 1151 RHC_ADDR1 = (sig_gen_buff_addr, sc_int<7>(0)); 1152 RHC_ADDR2 = 0; 1153 RHC_SIZE = ((sc_int<1>(0), DID_reg), sc_int<1>(0)); 1154 RHC_OP_CODE = -3; 1155 RHC_OP_START = 1; 1156 wait(); 1157 while(!RHC_OP_END.read()) { 1158 wait(); 1159 continue; 1160 } 1161 wait(); 1162 RHC_OP_START = 0; 1163 wait(); 1164 RHC_ADDR1 = 3779; 1165 RHC_ADDR2 = 0; 1166 RHC_SIZE = sig_gen_buff_addr; 1167 RHC_OP_CODE = -2; 1168 RHC_OP_START = 1; 1169 wait(); 1170 while(!RHC_OP_END.read()) { 1171 wait(); 1172 continue; 1173 } 1174 wait(); 1175 RHC_OP_START = 0; 1176 wait(); 1177 atemp = (sig_gen_buff_addr, sc_int<7>(10)); 1178 dt = (dtemp.range(15,5), RP_addr_ptr.range(4,0)); 1179 EXC_ADDR = atemp; 1180 EXC_DATA = dt; 1181 EXC_RW = 0; 1182 EXC_REQ = 1; 1183 wait(); 1184 while(1) { 1185 EXC_REQ = 0; 1186 if(IBC_GRANT_EXC) { 1187 wait(); 1188 break; 1189 } 1190 wait(); 1191 } 1192 atemp = (sc_int<6>(0), RP_addr_ptr); 1193 EXC_ADDR = atemp; 1194 EXC_RPBH_ID = id_reg; 1195 EXC_RW = 1; 1196 EXC_REQ = 1; 1197 wait(); 1198 while(1) { 1199 dtemp = IBC_DATA.read(); 1200 EXC_REQ = 0; 1201 if(IBC_GRANT_EXC) { 1202 wait(); 1203 break; 1204 } 1205 wait(); 1206 } 1207 atemp = (sig_gen_buff_addr, sc_int<7>(11)); 1208 if(!(dtemp[1])) { 1209 dt = 0; 1210 } else { 1211 dt = 1; 1212 } 1213 EXC_ADDR = atemp; 1214 EXC_DATA = dt; 1215 EXC_RW = 0; 1216 EXC_REQ = 1; 1217 wait(); 1218 while(1) { 1219 EXC_REQ = 0; 1220 if(IBC_GRANT_EXC) { 1221 wait(); 1222 break; 1223 } 1224 wait(); 1225 } 1226 atemp = atemp_1; 1227 EXC_ADDR = atemp; 1228 EXC_RPBH_ID = id_reg; 1229 EXC_RW = 1; 1230 EXC_REQ = 1; 1231 wait(); 1232 while(1) { 1233 dtemp = IBC_DATA.read(); 1234 EXC_REQ = 0; 1235 if(IBC_GRANT_EXC) { 1236 wait(); 1237 break; 1238 } 1239 wait(); 1240 } 1241 atemp = (sig_gen_buff_addr, sc_int<7>(12)); 1242 dt = dtemp; 1243 EXC_ADDR = atemp; 1244 EXC_DATA = dt; 1245 EXC_RW = 0; 1246 EXC_REQ = 1; 1247 wait(); 1248 while(1) { 1249 EXC_REQ = 0; 1250 if(IBC_GRANT_EXC) { 1251 wait(); 1252 break; 1253 } 1254 wait(); 1255 } 1256 RHC_ADDR1 = atemp_3; 1257 RHC_ADDR2 = (sig_gen_buff_addr, sc_int<7>(0)); 1258 RHC_OP_CODE = 1; 1259 EXC_RPBH_ID = id_reg; 1260 RHC_OP_START = 1; 1261 wait(); 1262 while(!RHC_OP_END.read()) { 1263 wait(); 1264 continue; 1265 } 1266 wait(); 1267 RHC_OP_START = 0; 1268 wait(); 1269 break; 1270 // } else { 1271 default: 1272 err_no_reg = -4; 1273 rb_flag = 1; 1274 wait(); 1275 } // end _case_1396_ 1276 1277 // } else if(208 == _case_1021_) { 1278 case 208: 1279 if(((MET_reg) != 3) || ((DID_reg) == 0)) { 1280 err_no_reg = 1; 1281 rb_flag = 1; 1282 wait(); 1283 } else { 1284 wait(); 1285 err_no_reg = err_no_reg; 1286 rb_flag = rb_flag; 1287 atemp = (sig_gen_buff_addr, sc_int<7>(24)); 1288 EXC_ADDR = atemp; 1289 EXC_RPBH_ID = id_reg; 1290 EXC_RW = 1; 1291 EXC_REQ = 1; 1292 wait(); 1293 while(1) { 1294 dtemp = IBC_DATA.read(); 1295 EXC_REQ = 0; 1296 if(IBC_GRANT_EXC) { 1297 wait(); 1298 break; 1299 } 1300 wait(); 1301 } 1302 NHW_reg = dtemp.range(13,8); 1303 Data_Start_reg = (NHW_reg) + 2; 1304 atemp = (sig_gen_buff_addr, sc_int<7>(8)); 1305 dt = dtemp; 1306 EXC_ADDR = atemp; 1307 EXC_DATA = dt; 1308 EXC_RW = 0; 1309 EXC_REQ = 1; 1310 wait(); 1311 while(1) { 1312 EXC_REQ = 0; 1313 if(IBC_GRANT_EXC) { 1314 wait(); 1315 break; 1316 } 1317 wait(); 1318 } 1319 atemp = (sig_gen_buff_addr, sc_int<7>(25)); 1320 EXC_ADDR = atemp; 1321 EXC_RPBH_ID = id_reg; 1322 EXC_RW = 1; 1323 EXC_REQ = 1; 1324 wait(); 1325 while(1) { 1326 dtemp = IBC_DATA.read(); 1327 EXC_REQ = 0; 1328 if(IBC_GRANT_EXC) { 1329 wait(); 1330 break; 1331 } 1332 wait(); 1333 } 1334 total_data_len = dtemp.range(11,0); 1335 atemp = (sig_gen_buff_addr, sc_int<7>(9)); 1336 dt = dtemp; 1337 EXC_ADDR = atemp; 1338 EXC_DATA = dt; 1339 EXC_RW = 0; 1340 EXC_REQ = 1; 1341 wait(); 1342 while(1) { 1343 EXC_REQ = 0; 1344 if(IBC_GRANT_EXC) { 1345 wait(); 1346 break; 1347 } 1348 wait(); 1349 } 1350 Data_Start_reg = 32 + ((Data_Start_reg) << 1); 1351 MET_reg = 6; 1352 if(DID_reg[0]) { 1353 DID_reg = 10; 1354 atemp_1 = 272; 1355 } else { 1356 DID_reg = 11; 1357 atemp_1 = 288; 1358 } 1359 atemp = (sig_gen_buff_addr, sc_int<7>(0)); 1360 dt = ((Data_Start_reg, MET_reg), DID_reg); 1361 EXC_ADDR = atemp; 1362 EXC_DATA = dt; 1363 EXC_RW = 0; 1364 EXC_REQ = 1; 1365 wait(); 1366 while(1) { 1367 EXC_REQ = 0; 1368 if(IBC_GRANT_EXC) { 1369 wait(); 1370 break; 1371 } 1372 wait(); 1373 } 1374 atemp = (sig_gen_buff_addr, sc_int<7>(1)); 1375 dt = (sc_int<4>(0), total_data_len); 1376 EXC_ADDR = atemp; 1377 EXC_DATA = dt; 1378 EXC_RW = 0; 1379 EXC_REQ = 1; 1380 wait(); 1381 while(1) { 1382 EXC_REQ = 0; 1383 if(IBC_GRANT_EXC) { 1384 wait(); 1385 break; 1386 } 1387 wait(); 1388 } 1389 RHC_ADDR1 = (sig_gen_buff_addr, sc_int<7>(26)); 1390 RHC_ADDR2 = (sig_gen_buff_addr, sc_int<7>(10)); 1391 RHC_SIZE = NHW_reg; 1392 RHC_OP_CODE = 3; 1393 EXC_RPBH_ID = id_reg; 1394 RHC_OP_START = 1; 1395 wait(); 1396 while(!RHC_OP_END.read()) { 1397 wait(); 1398 continue; 1399 } 1400 wait(); 1401 RHC_OP_START = 0; 1402 wait(); 1403 RHC_ADDR1 = atemp_1; 1404 RHC_ADDR2 = (sig_gen_buff_addr, sc_int<7>(0)); 1405 RHC_OP_CODE = 1; 1406 EXC_RPBH_ID = id_reg; 1407 RHC_OP_START = 1; 1408 wait(); 1409 while(!RHC_OP_END.read()) { 1410 wait(); 1411 continue; 1412 } 1413 wait(); 1414 RHC_OP_START = 0; 1415 wait(); 1416 } 1417 break; 1418 // } else if(9 == _case_1021_) { 1419 case 9: 1420 if(((MET_reg) != 3) || ((DID_reg) == 0)) { 1421 err_no_reg = 1; 1422 rb_flag = 1; 1423 wait(); 1424 } else { 1425 wait(); 1426 err_no_reg = err_no_reg; 1427 rb_flag = rb_flag; 1428 Data_Start_reg = -32; 1429 MET_reg = 5; 1430 total_data_len = 2; 1431 LEV_reg = 0; 1432 NHW_reg = 3; 1433 RSN_reg = 9; 1434 DT_reg = 0; 1435 link_ptr = 0; 1436 V_reg = 0; 1437 if(DID_reg[0]) { 1438 DID_reg = 10; 1439 atemp_1 = 272; 1440 } else { 1441 DID_reg = 11; 1442 atemp_1 = 288; 1443 } 1444 atemp = (sig_gen_buff_addr, sc_int<7>(10)); 1445 EXC_ADDR = atemp; 1446 EXC_RPBH_ID = id_reg; 1447 EXC_RW = 1; 1448 EXC_REQ = 1; 1449 wait(); 1450 while(1) { 1451 dtemp = IBC_DATA.read(); 1452 EXC_REQ = 0; 1453 if(IBC_GRANT_EXC) { 1454 wait(); 1455 break; 1456 } 1457 wait(); 1458 } 1459 if((TM_EXC_FIR.read())[3]) { 1460 dtemp = 4096; 1461 } else { 1462 dtemp = dtemp; 1463 } 1464 wait(); 1465 _case_1934_ = dtemp; 1466 switch((int)_case_1934_) { 1467 case 0: 1468 // if(0 == _case_1934_) { 1469 atemp = (sig_gen_buff_addr, sc_int<7>(24)); 1470 dt = (256, MODE_S_P.read()); 1471 EXC_ADDR = atemp; 1472 EXC_DATA = dt; 1473 EXC_RW = 0; 1474 EXC_REQ = 1; 1475 wait(); 1476 while(1) { 1477 EXC_REQ = 0; 1478 if(IBC_GRANT_EXC) { 1479 wait(); 1480 break; 1481 } 1482 wait(); 1483 } break; 1484 // } else if(1 == _case_1934_) { 1485 case 1: 1486 atemp = (sig_gen_buff_addr, sc_int<7>(24)); 1487 dt = 3; 1488 EXC_ADDR = atemp; 1489 EXC_DATA = dt; 1490 EXC_RW = 0; 1491 EXC_REQ = 1; 1492 wait(); 1493 while(1) { 1494 EXC_REQ = 0; 1495 if(IBC_GRANT_EXC) { 1496 wait(); 1497 break; 1498 } 1499 wait(); 1500 } break; 1501 // } else if(2 == _case_1934_) { 1502 case 2: 1503 atemp = (sig_gen_buff_addr, sc_int<7>(24)); 1504 dt = 32; 1505 EXC_ADDR = atemp; 1506 EXC_DATA = dt; 1507 EXC_RW = 0; 1508 EXC_REQ = 1; 1509 wait(); 1510 while(1) { 1511 EXC_REQ = 0; 1512 if(IBC_GRANT_EXC) { 1513 wait(); 1514 break; 1515 } 1516 wait(); 1517 } break; 1518 // } else if(3 == _case_1934_) { 1519 case 3: 1520 atemp = (sig_gen_buff_addr, sc_int<7>(24)); 1521 dt = ( sc_int<10>(0), ( RPBI_BPA.read() , RPBI_APA.read() ) ); 1522 EXC_ADDR = atemp; 1523 EXC_DATA = dt; 1524 EXC_RW = 0; 1525 EXC_REQ = 1; 1526 wait(); 1527 while(1) { 1528 EXC_REQ = 0; 1529 if(IBC_GRANT_EXC) { 1530 wait(); 1531 break; 1532 } 1533 wait(); 1534 } break; 1535 // } else if(4 == _case_1934_) { 1536 case 4: 1537 total_data_len = 6; 1538 if(!(DID_reg[0])) { 1539 RHC_ADDR1 = 8; 1540 } else { 1541 RHC_ADDR1 = 16; 1542 } 1543 RHC_ADDR2 = (sig_gen_buff_addr, sc_int<7>(24)); 1544 RHC_SIZE = 3; 1545 RHC_OP_CODE = 3; 1546 EXC_RPBH_ID = id_reg; 1547 RHC_OP_START = 1; 1548 wait(); 1549 while(!RHC_OP_END.read()) { 1550 wait(); 1551 continue; 1552 } 1553 wait(); 1554 RHC_OP_START = 0; 1555 wait(); break; 1556 // } else if(5 == _case_1934_) { 1557 case 5: 1558 total_data_len = 64; 1559 if(!(DID_reg[0])) { 1560 RHC_ADDR1 = 64; 1561 } else { 1562 RHC_ADDR1 = 96; 1563 } 1564 RHC_ADDR2 = (sig_gen_buff_addr, sc_int<7>(24)); 1565 RHC_SIZE = 32; 1566 RHC_OP_CODE = 3; 1567 EXC_RPBH_ID = id_reg; 1568 RHC_OP_START = 1; 1569 wait(); 1570 while(!RHC_OP_END.read()) { 1571 wait(); 1572 continue; 1573 } 1574 wait(); 1575 RHC_OP_START = 0; 1576 wait(); break; 1577 // } else if(6 == _case_1934_) { 1578 case 6: 1579 total_data_len = 64; 1580 if(!(DID_reg[0])) { 1581 RHC_ADDR1 = 128; 1582 } else { 1583 RHC_ADDR1 = 160; 1584 } 1585 RHC_ADDR2 = (sig_gen_buff_addr, sc_int<7>(24)); 1586 RHC_SIZE = 32; 1587 RHC_OP_CODE = 3; 1588 EXC_RPBH_ID = id_reg; 1589 RHC_OP_START = 1; 1590 wait(); 1591 while(!RHC_OP_END.read()) { 1592 wait(); 1593 continue; 1594 } 1595 wait(); 1596 RHC_OP_START = 0; 1597 wait(); break; 1598 // } else if(7 == _case_1934_) { 1599 case 7: 1600 if(!MODE_S_P.read()) { 1601 total_data_len = 12; 1602 RHC_SIZE = 6; 1603 } else { 1604 total_data_len = 8; 1605 RHC_SIZE = 4; 1606 } 1607 if(!(DID_reg[0])) { 1608 RHC_ADDR1 = 32; 1609 } else { 1610 RHC_ADDR1 = 48; 1611 } 1612 RHC_ADDR2 = (sig_gen_buff_addr, sc_int<7>(24)); 1613 RHC_OP_CODE = 3; 1614 EXC_RPBH_ID = id_reg; 1615 RHC_OP_START = 1; 1616 wait(); 1617 while(!RHC_OP_END.read()) { 1618 wait(); 1619 continue; 1620 } 1621 wait(); 1622 RHC_OP_START = 0; 1623 wait(); break; 1624 // } else if(8 == _case_1934_) { 1625 case 8: 1626 total_data_len = 2; 1627 if(!(DID_reg[0])) { 1628 RHC_ADDR1 = 2; 1629 } else { 1630 RHC_ADDR1 = 4; 1631 } 1632 RHC_ADDR2 = (sig_gen_buff_addr, sc_int<7>(24)); 1633 RHC_SIZE = 1; 1634 RHC_OP_CODE = 3; 1635 EXC_RPBH_ID = id_reg; 1636 RHC_OP_START = 1; 1637 wait(); 1638 while(!RHC_OP_END.read()) { 1639 wait(); 1640 continue; 1641 } 1642 wait(); 1643 RHC_OP_START = 0; 1644 wait(); break; 1645 // } else if(9 == _case_1934_) { 1646 case 9: 1647 total_data_len = 8; 1648 RHC_ADDR1 = 20; 1649 RHC_ADDR2 = (sig_gen_buff_addr, sc_int<7>(24)); 1650 RHC_SIZE = 4; 1651 RHC_OP_CODE = 3; 1652 EXC_RPBH_ID = id_reg; 1653 RHC_OP_START = 1; 1654 wait(); 1655 while(!RHC_OP_END.read()) { 1656 wait(); 1657 continue; 1658 } 1659 wait(); 1660 RHC_OP_START = 0; 1661 wait(); break; 1662 // } else if(10 == _case_1934_) { 1663 case 10: 1664 total_data_len = 2; 1665 if(!(DID_reg[0])) { 1666 atemp_2 = 0; 1667 } else { 1668 atemp_2 = 1; 1669 } 1670 RHC_ADDR1 = atemp_2; 1671 RHC_ADDR2 = (sig_gen_buff_addr, sc_int<7>(24)); 1672 RHC_SIZE = 1; 1673 RHC_OP_CODE = 3; 1674 EXC_RPBH_ID = id_reg; 1675 RHC_OP_START = 1; 1676 wait(); 1677 while(!RHC_OP_END.read()) { 1678 wait(); 1679 continue; 1680 } 1681 wait(); 1682 RHC_OP_START = 0; 1683 wait(); 1684 atemp = atemp_2; 1685 dt = 0; 1686 EXC_ADDR = atemp; 1687 EXC_DATA = dt; 1688 EXC_RW = 0; 1689 EXC_REQ = 1; 1690 wait(); 1691 while(1) { 1692 EXC_REQ = 0; 1693 if(IBC_GRANT_EXC) { 1694 wait(); 1695 break; 1696 } 1697 wait(); 1698 } break; 1699 // } else if(-1 == _case_1934_) { 1700 case -1: 1701 index = 0; 1702 GB_1_ind = 1; 1703 atemp = (sig_gen_buff_addr, sc_int<7>(11)); 1704 EXC_ADDR = atemp; 1705 EXC_RPBH_ID = id_reg; 1706 EXC_RW = 1; 1707 EXC_REQ = 1; 1708 wait(); 1709 while(1) { 1710 dtemp = IBC_DATA.read(); 1711 EXC_REQ = 0; 1712 if(IBC_GRANT_EXC) { 1713 wait(); 1714 break; 1715 } 1716 wait(); 1717 } 1718 atemp_2 = dtemp.range(13,0); 1719 atemp_3 = (sig_gen_buff_addr, sc_int<7>(24)); 1720 atemp = (sig_gen_buff_addr, sc_int<7>(13)); 1721 EXC_ADDR = atemp; 1722 EXC_RPBH_ID = id_reg; 1723 EXC_RW = 1; 1724 EXC_REQ = 1; 1725 wait(); 1726 while(1) { 1727 dtemp = IBC_DATA.read(); 1728 EXC_REQ = 0; 1729 if(IBC_GRANT_EXC) { 1730 wait(); 1731 break; 1732 } 1733 wait(); 1734 } 1735 cnt = dtemp.range(11,0); 1736 total_data_len = dtemp.range(11,0); 1737 dtemp_1 = -48; 1738 mem_copy_op_1: while(1) { 1739 if((cnt) <= 1) { 1740 index = 0; 1741 wait(); 1742 break; 1743 } else { 1744 wait(); 1745 } 1746 if(cnt > (dtemp_1)) { 1747 index = dtemp_1.range(7,1); 1748 GB_ext_flg = 1; 1749 cnt = cnt - (dtemp_1); 1750 } else { 1751 index = cnt.range(7,1); 1752 GB_ext_flg = 0; 1753 cnt = cnt & 1; 1754 } 1755 RHC_ADDR1 = atemp_2; 1756 RHC_ADDR2 = atemp_3; 1757 RHC_SIZE = index; 1758 RHC_OP_CODE = 3; 1759 EXC_RPBH_ID = id_reg; 1760 RHC_OP_START = 1; 1761 wait(); 1762 while(!RHC_OP_END.read()) { 1763 wait(); 1764 continue; 1765 } 1766 wait(); 1767 RHC_OP_START = 0; 1768 wait(); 1769 if(!GB_ext_flg) { 1770 wait(); 1771 break; 1772 } else { 1773 wait(); 1774 } 1775 EXC_ADDR = -8192; 1776 EXC_RPBH_ID = id_reg; 1777 EXC_RW = 1; 1778 EXC_REQ = 1; 1779 wait(); 1780 while(1) { 1781 dtemp = IBC_DATA.read(); 1782 EXC_REQ = 0; 1783 if(IBC_GRANT_EXC) { 1784 wait(); 1785 break; 1786 } 1787 wait(); 1788 } 1789 if(GB_1_ind) { 1790 link_ptr = dtemp.range(13,7); 1791 V_reg = 1; 1792 atemp = atemp; 1793 dt = dt; 1794 wait(); 1795 } else { 1796 link_ptr = link_ptr; 1797 V_reg = V_reg; 1798 atemp = (atemp_4.range(13,7), sc_int<7>(2)); 1799 dt = (sc_int<3>(-4), dtemp.range(12,0)); 1800 EXC_ADDR = atemp; 1801 EXC_DATA = dt; 1802 EXC_RW = 0; 1803 EXC_REQ = 1; 1804 wait(); 1805 while(1) { 1806 EXC_REQ = 0; 1807 if(IBC_GRANT_EXC) { 1808 wait(); 1809 break; 1810 } 1811 wait(); 1812 } 1813 } 1814 dtemp_1 = -16; 1815 atemp_2 = atemp_2 + (index); 1816 atemp_3 = (dtemp.range(13,7), sc_int<7>(8)); 1817 atemp_4 = dtemp.range(13,0); 1818 GB_1_ind = 0; 1819 } 1820 if(!(cnt[0])) { 1821 wait(); 1822 } else { 1823 wait(); 1824 atemp = atemp_2 + (index); 1825 EXC_ADDR = atemp; 1826 EXC_RPBH_ID = id_reg; 1827 EXC_RW = 1; 1828 EXC_REQ = 1; 1829 wait(); 1830 while(1) { 1831 dtemp = IBC_DATA.read(); 1832 EXC_REQ = 0; 1833 if(IBC_GRANT_EXC) { 1834 wait(); 1835 break; 1836 } 1837 wait(); 1838 } 1839 atemp = atemp_3 + (index); 1840 dt = (sc_int<8>(0), dtemp.range(7,0)); 1841 EXC_ADDR = atemp; 1842 EXC_DATA = dt; 1843 EXC_RW = 0; 1844 EXC_REQ = 1; 1845 wait(); 1846 while(1) { 1847 EXC_REQ = 0; 1848 if(IBC_GRANT_EXC) { 1849 wait(); 1850 break; 1851 } 1852 wait(); 1853 } 1854 } 1855 if(!GB_1_ind) { 1856 atemp = (atemp_4.range(13,7), sc_int<7>(2)); 1857 dt = 0; 1858 EXC_ADDR = atemp; 1859 EXC_DATA = dt; 1860 EXC_RW = 0; 1861 EXC_REQ = 1; 1862 wait(); 1863 while(1) { 1864 EXC_REQ = 0; 1865 if(IBC_GRANT_EXC) { 1866 wait(); 1867 break; 1868 } 1869 wait(); 1870 } 1871 } else { 1872 wait(); 1873 } break; 1874 // } else { 1875 default: 1876 err_no_reg = -3; 1877 rb_flag = 1; 1878 wait(); 1879 } // end _case_1934_ 1880 if((rb_flag) == 0) { 1881 wait(); 1882 RHC_ADDR1 = (sig_gen_buff_addr, link_ptr); 1883 RHC_ADDR2 = (sc_int<2>(0), total_data_len); 1884 RHC_SIZE = ((sc_int<1>(0), DID_reg), V_reg); 1885 RHC_OP_CODE = -3; 1886 RHC_OP_START = 1; 1887 wait(); 1888 while(!RHC_OP_END.read()) { 1889 wait(); 1890 continue; 1891 } 1892 wait(); 1893 RHC_OP_START = 0; 1894 wait(); 1895 RHC_ADDR1 = (sc_int<8>(9), NHW_reg); 1896 RHC_ADDR2 = (sc_int<2>(0), total_data_len); 1897 RHC_SIZE = sig_gen_buff_addr; 1898 RHC_OP_CODE = -2; 1899 RHC_OP_START = 1; 1900 wait(); 1901 while(!RHC_OP_END.read()) { 1902 wait(); 1903 continue; 1904 } 1905 wait(); 1906 RHC_OP_START = 0; 1907 wait(); 1908 RHC_ADDR1 = atemp_1; 1909 RHC_ADDR2 = (sig_gen_buff_addr, sc_int<7>(0)); 1910 RHC_OP_CODE = 1; 1911 EXC_RPBH_ID = id_reg; 1912 RHC_OP_START = 1; 1913 wait(); 1914 while(!RHC_OP_END.read()) { 1915 wait(); 1916 continue; 1917 } 1918 wait(); 1919 RHC_OP_START = 0; 1920 wait(); 1921 } else { 1922 wait(); 1923 } 1924 } 1925 break; 1926 // } else if(210 == _case_1021_) { 1927 case 210: 1928 if(((MET_reg) != 3) || ((DID_reg) == 0)) { 1929 err_no_reg = 1; 1930 rb_flag = 1; 1931 wait(); 1932 } else { 1933 wait(); 1934 err_no_reg = err_no_reg; 1935 rb_flag = 1; 1936 atemp = (sig_gen_buff_addr, sc_int<7>(1)); 1937 EXC_ADDR = atemp; 1938 EXC_RPBH_ID = id_reg; 1939 EXC_RW = 1; 1940 EXC_REQ = 1; 1941 wait(); 1942 while(1) { 1943 dtemp = IBC_DATA.read(); 1944 EXC_REQ = 0; 1945 if(IBC_GRANT_EXC) { 1946 wait(); 1947 break; 1948 } 1949 wait(); 1950 } 1951 cnt = dtemp.range(11,0); 1952 atemp = (sig_gen_buff_addr, sc_int<7>(10)); 1953 EXC_ADDR = atemp; 1954 EXC_RPBH_ID = id_reg; 1955 EXC_RW = 1; 1956 EXC_REQ = 1; 1957 wait(); 1958 while(1) { 1959 dtemp = IBC_DATA.read(); 1960 EXC_REQ = 0; 1961 if(IBC_GRANT_EXC) { 1962 wait(); 1963 break; 1964 } 1965 wait(); 1966 } 1967 if((TM_EXC_FIR.read())[3]) { 1968 dtemp = 4096; 1969 } else { 1970 dtemp = dtemp; 1971 } 1972 wait(); 1973 _case_2503_ = dtemp; 1974 switch((int)_case_2503_) { 1975 // if(4 == _case_2503_) { 1976 case 4: 1977 if((cnt) != 6) { 1978 err_no_reg = 2; 1979 wait(); 1980 } else { 1981 atemp = (sig_gen_buff_addr, sc_int<7>(24)); 1982 EXC_ADDR = atemp; 1983 EXC_RPBH_ID = id_reg; 1984 EXC_RW = 1; 1985 EXC_REQ = 1; 1986 wait(); 1987 while(1) { 1988 dtemp = IBC_DATA.read(); 1989 EXC_REQ = 0; 1990 if(IBC_GRANT_EXC) { 1991 wait(); 1992 break; 1993 } 1994 wait(); 1995 } 1996 dt = (sc_int<1>(1), dtemp.range(14,0)); 1997 if(DID_reg[0]) { 1998 atemp = 8; 1999 atemp_1 = 9; 2000 } else { 2001 atemp = 16; 2002 atemp_1 = 17; 2003 } 2004 EXC_ADDR = atemp; 2005 EXC_DATA = dt; 2006 EXC_RW = 0; 2007 EXC_REQ = 1; 2008 wait(); 2009 while(1) { 2010 EXC_REQ = 0; 2011 if(IBC_GRANT_EXC) { 2012 wait(); 2013 break; 2014 } 2015 wait(); 2016 } 2017 RHC_ADDR1 = (sig_gen_buff_addr, sc_int<7>(25)); 2018 RHC_ADDR2 = atemp_1; 2019 RHC_SIZE = 2; 2020 RHC_OP_CODE = 3; 2021 EXC_RPBH_ID = id_reg; 2022 RHC_OP_START = 1; 2023 wait(); 2024 while(!RHC_OP_END.read()) { 2025 wait(); 2026 continue; 2027 } 2028 wait(); 2029 RHC_OP_START = 0; 2030 wait(); 2031 } break; 2032 // } else if(5 == _case_2503_) { 2033 case 5: 2034 if((cnt) != 64) { 2035 err_no_reg = 2; 2036 wait(); 2037 } else { 2038 RHC_ADDR1 = (sig_gen_buff_addr, sc_int<7>(24)); 2039 RHC_SIZE = 32; 2040 if(DID_reg[0]) { 2041 RHC_ADDR2 = 64; 2042 } else { 2043 RHC_ADDR2 = 96; 2044 } 2045 RHC_OP_CODE = 3; 2046 EXC_RPBH_ID = id_reg; 2047 RHC_OP_START = 1; 2048 wait(); 2049 while(!RHC_OP_END.read()) { 2050 wait(); 2051 continue; 2052 } 2053 wait(); 2054 RHC_OP_START = 0; 2055 wait(); 2056 } break; 2057 // } else if(6 == _case_2503_) { 2058 case 6: 2059 if((cnt) != 64) { 2060 err_no_reg = 2; 2061 wait(); 2062 } else { 2063 RHC_ADDR1 = (sig_gen_buff_addr, sc_int<7>(24)); 2064 RHC_SIZE = 32; 2065 if(DID_reg[0]) { 2066 RHC_ADDR2 = 128; 2067 } else { 2068 RHC_ADDR2 = 160; 2069 } 2070 RHC_OP_CODE = 3; 2071 EXC_RPBH_ID = id_reg; 2072 RHC_OP_START = 1; 2073 wait(); 2074 while(!RHC_OP_END.read()) { 2075 wait(); 2076 continue; 2077 } 2078 wait(); 2079 RHC_OP_START = 0; 2080 wait(); 2081 } break; 2082 // } else if(7 == _case_2503_) { 2083 case 7: 2084 if(((!MODE_S_P.read()) && ((cnt) != 12)) || (MODE_S_P.read() && ((cnt) != 8))) { 2085 err_no_reg = 2; 2086 wait(); 2087 } else { 2088 RHC_ADDR1 = (sig_gen_buff_addr, sc_int<7>(24)); 2089 if(!MODE_S_P.read()) { 2090 RHC_SIZE = 6; 2091 } else { 2092 RHC_SIZE = 4; 2093 } 2094 if(DID_reg[0]) { 2095 RHC_ADDR2 = 32; 2096 } else { 2097 RHC_ADDR2 = 48; 2098 } 2099 RHC_OP_CODE = 3; 2100 EXC_RPBH_ID = id_reg; 2101 RHC_OP_START = 1; 2102 wait(); 2103 while(!RHC_OP_END.read()) { 2104 wait(); 2105 continue; 2106 } 2107 wait(); 2108 RHC_OP_START = 0; 2109 wait(); 2110 } break; 2111 // } else if(8 == _case_2503_) { 2112 case 8: 2113 if((cnt) != 2) { 2114 err_no_reg = 2; 2115 wait(); 2116 } else { 2117 atemp = (sig_gen_buff_addr, sc_int<7>(24)); 2118 if(DID_reg[0]) { 2119 atemp_1 = 2; 2120 } else { 2121 atemp_1 = 4; 2122 } 2123 RHC_ADDR1 = atemp; 2124 RHC_ADDR2 = atemp_1; 2125 RHC_SIZE = 1; 2126 RHC_OP_CODE = 3; 2127 EXC_RPBH_ID = id_reg; 2128 RHC_OP_START = 1; 2129 wait(); 2130 while(!RHC_OP_END.read()) { 2131 wait(); 2132 continue; 2133 } 2134 wait(); 2135 RHC_OP_START = 0; 2136 wait(); 2137 } break; 2138 // } else if(9 == _case_2503_) { 2139 case 9: 2140 if((cnt) != 8) { 2141 err_no_reg = 2; 2142 wait(); 2143 } else { 2144 RHC_ADDR1 = (sig_gen_buff_addr, sc_int<7>(24)); 2145 RHC_ADDR2 = 20; 2146 RHC_SIZE = 4; 2147 RHC_OP_CODE = 3; 2148 EXC_RPBH_ID = id_reg; 2149 RHC_OP_START = 1; 2150 wait(); 2151 while(!RHC_OP_END.read()) { 2152 wait(); 2153 continue; 2154 } 2155 wait(); 2156 RHC_OP_START = 0; 2157 wait(); 2158 } break; 2159 // } else if(-1 == _case_2503_) { 2160 case -1: 2161 wt_mem: do { 2162 atemp = (sig_gen_buff_addr, sc_int<7>(11)); 2163 EXC_ADDR = atemp; 2164 EXC_RPBH_ID = id_reg; 2165 EXC_RW = 1; 2166 EXC_REQ = 1; 2167 wait(); 2168 while(1) { 2169 dtemp = IBC_DATA.read(); 2170 EXC_REQ = 0; 2171 if(IBC_GRANT_EXC) { 2172 wait(); 2173 break; 2174 } 2175 wait(); 2176 } 2177 atemp_2 = dtemp.range(13,0); 2178 atemp_1 = (sig_gen_buff_addr, sc_int<7>(24)); 2179 GB_copy_op_1: while(1) { 2180 if((cnt) <= 1) { 2181 wait(); 2182 break; 2183 } else { 2184 atemp = atemp_1; 2185 EXC_ADDR = atemp; 2186 EXC_RPBH_ID = id_reg; 2187 EXC_RW = 1; 2188 EXC_REQ = 1; 2189 wait(); 2190 while(1) { 2191 dtemp = IBC_DATA.read(); 2192 EXC_REQ = 0; 2193 if(IBC_GRANT_EXC) { 2194 wait(); 2195 break; 2196 } 2197 wait(); 2198 } 2199 atemp = atemp_2; 2200 dt = dtemp; 2201 EXC_ADDR = atemp; 2202 EXC_DATA = dt; 2203 EXC_RW = 0; 2204 EXC_REQ = 1; 2205 wait(); 2206 while(1) { 2207 EXC_REQ = 0; 2208 if(IBC_GRANT_EXC) { 2209 wait(); 2210 break; 2211 } 2212 wait(); 2213 } 2214 atemp_1 = (atemp_1) + 1; 2215 atemp_2 = (atemp_2) + 1; 2216 cnt = (cnt) - 2; 2217 if(atemp_1 <= ((sig_gen_buff_addr, sc_int<7>(-1)))) { 2218 wait(); 2219 continue; 2220 } else { 2221 atemp = (sig_gen_buff_addr, sc_int<7>(2)); 2222 EXC_ADDR = atemp; 2223 EXC_RPBH_ID = id_reg; 2224 EXC_RW = 1; 2225 EXC_REQ = 1; 2226 wait(); 2227 while(1) { 2228 dtemp = IBC_DATA.read(); 2229 EXC_REQ = 0; 2230 if(IBC_GRANT_EXC) { 2231 wait(); 2232 break; 2233 } 2234 wait(); 2235 } 2236 dt = ((sc_int<1>(0), sig_gen_buff_addr), sc_int<8>(0)); 2237 EXC_ADDR = -8192; 2238 EXC_DATA = dt; 2239 EXC_RW = 0; 2240 EXC_REQ = 1; 2241 wait(); 2242 while(1) { 2243 EXC_REQ = 0; 2244 if(IBC_GRANT_EXC) { 2245 wait(); 2246 break; 2247 } 2248 wait(); 2249 } 2250 sig_gen_buff_addr = dtemp.range(13,7); 2251 atemp_1 = (sig_gen_buff_addr, sc_int<7>(8)); 2252 } 2253 } 2254 } 2255 if(!(cnt[0])) { 2256 wait(); 2257 break; //goto _wt_mem__END; 2258 } else { 2259 atemp = atemp_1; 2260 EXC_ADDR = atemp; 2261 EXC_RPBH_ID = id_reg; 2262 EXC_RW = 1; 2263 EXC_REQ = 1; 2264 wait(); 2265 while(1) { 2266 dtemp = IBC_DATA.read(); 2267 EXC_REQ = 0; 2268 if(IBC_GRANT_EXC) { 2269 wait(); 2270 break; 2271 } 2272 wait(); 2273 } 2274 atemp_3.range(7,0) = dtemp.range(7,0); 2275 atemp = atemp_2; 2276 EXC_ADDR = atemp; 2277 EXC_RPBH_ID = id_reg; 2278 EXC_RW = 1; 2279 EXC_REQ = 1; 2280 wait(); 2281 while(1) { 2282 dtemp = IBC_DATA.read(); 2283 EXC_REQ = 0; 2284 if(IBC_GRANT_EXC) { 2285 wait(); 2286 break; 2287 } 2288 wait(); 2289 } 2290 dt = (dtemp.range(15,8), atemp_3.range(7,0)); 2291 EXC_ADDR = atemp; 2292 EXC_DATA = dt; 2293 EXC_RW = 0; 2294 EXC_REQ = 1; 2295 wait(); 2296 while(1) { 2297 EXC_REQ = 0; 2298 if(IBC_GRANT_EXC) { 2299 wait(); 2300 break; 2301 } 2302 wait(); 2303 } 2304 } 2305 _wt_mem__END:; }while(0); 2306 break; 2307 // } else { 2308 default: 2309 err_no_reg = -3; 2310 wait(); 2311 } // end _case_2503_ 2312 } 2313 break; 2314 // } else if(176 == _case_1021_) { 2315 case 176: 2316 if(((MET_reg) != 3) || ((DID_reg) != 0)) { 2317 err_no_reg = 1; 2318 rb_flag = 1; 2319 wait(); 2320 } else { 2321 wait(); 2322 rb_flag = rb_flag; 2323 id_reg = 1; 2324 if(!MODE_S_P.read()) { 2325 total_data_len = 156; 2326 } else { 2327 total_data_len = 152; 2328 } 2329 RSN_reg = 10; 2330 RHC_ADDR1 = (sig_gen_buff_addr, sc_int<7>(0)); 2331 RHC_ADDR2 = (sc_int<2>(0), total_data_len); 2332 RHC_SIZE = 20; 2333 RHC_OP_CODE = -3; 2334 RHC_OP_START = 1; 2335 wait(); 2336 while(!RHC_OP_END.read()) { 2337 wait(); 2338 continue; 2339 } 2340 wait(); 2341 RHC_OP_START = 0; 2342 wait(); 2343 RHC_ADDR1 = (RSN_reg, sc_int<6>(1)); 2344 RHC_ADDR2 = (sc_int<2>(0), total_data_len); 2345 RHC_SIZE = sig_gen_buff_addr; 2346 RHC_OP_CODE = -2; 2347 RHC_OP_START = 1; 2348 wait(); 2349 while(!RHC_OP_END.read()) { 2350 wait(); 2351 continue; 2352 } 2353 wait(); 2354 RHC_OP_START = 0; 2355 wait(); 2356 atemp = (sig_gen_buff_addr, sc_int<7>(10)); 2357 dt = 0; 2358 EXC_ADDR = atemp; 2359 EXC_DATA = dt; 2360 EXC_RW = 0; 2361 EXC_REQ = 1; 2362 wait(); 2363 while(1) { 2364 EXC_REQ = 0; 2365 if(IBC_GRANT_EXC) { 2366 wait(); 2367 break; 2368 } 2369 wait(); 2370 } 2371 RHC_ADDR1 = 8; 2372 RHC_ADDR2 = (sig_gen_buff_addr, sc_int<7>(24)); 2373 RHC_SIZE = 3; 2374 RHC_OP_CODE = 3; 2375 EXC_RPBH_ID = id_reg; 2376 RHC_OP_START = 1; 2377 wait(); 2378 while(!RHC_OP_END.read()) { 2379 wait(); 2380 continue; 2381 } 2382 wait(); 2383 RHC_OP_START = 0; 2384 wait(); 2385 RHC_ADDR1 = 64; 2386 RHC_ADDR2 = (sig_gen_buff_addr, sc_int<7>(27)); 2387 RHC_SIZE = 32; 2388 RHC_OP_CODE = 3; 2389 EXC_RPBH_ID = id_reg; 2390 RHC_OP_START = 1; 2391 wait(); 2392 while(!RHC_OP_END.read()) { 2393 wait(); 2394 continue; 2395 } 2396 wait(); 2397 RHC_OP_START = 0; 2398 wait(); 2399 RHC_ADDR1 = 128; 2400 RHC_ADDR2 = (sig_gen_buff_addr, sc_int<7>(59)); 2401 RHC_OP_CODE = 3; 2402 EXC_RPBH_ID = id_reg; 2403 RHC_OP_START = 1; 2404 wait(); 2405 while(!RHC_OP_END.read()) { 2406 wait(); 2407 continue; 2408 } 2409 wait(); 2410 RHC_OP_START = 0; 2411 wait(); 2412 RHC_ADDR1 = 32; 2413 RHC_ADDR2 = (sig_gen_buff_addr, sc_int<7>(-37)); 2414 if(!MODE_S_P.read()) { 2415 atemp_1 = (sig_gen_buff_addr, sc_int<7>(-31)); 2416 atemp_2 = (sig_gen_buff_addr, sc_int<7>(-30)); 2417 atemp_3 = 6; 2418 RHC_SIZE = 6; 2419 } else { 2420 atemp_1 = (sig_gen_buff_addr, sc_int<7>(-33)); 2421 atemp_2 = (sig_gen_buff_addr, sc_int<7>(-32)); 2422 atemp_3 = 4; 2423 RHC_SIZE = 4; 2424 } 2425 RHC_OP_CODE = 3; 2426 EXC_RPBH_ID = id_reg; 2427 RHC_OP_START = 1; 2428 wait(); 2429 while(!RHC_OP_END.read()) { 2430 wait(); 2431 continue; 2432 } 2433 wait(); 2434 RHC_OP_START = 0; 2435 wait(); 2436 RHC_ADDR1 = 2; 2437 RHC_ADDR2 = atemp_1; 2438 RHC_SIZE = 1; 2439 RHC_OP_CODE = 3; 2440 EXC_RPBH_ID = id_reg; 2441 RHC_OP_START = 1; 2442 wait(); 2443 while(!RHC_OP_END.read()) { 2444 wait(); 2445 continue; 2446 } 2447 wait(); 2448 RHC_OP_START = 0; 2449 wait(); 2450 RHC_ADDR1 = 20; 2451 RHC_ADDR2 = atemp_2; 2452 RHC_SIZE = 4; 2453 RHC_OP_CODE = 3; 2454 EXC_RPBH_ID = id_reg; 2455 RHC_OP_START = 1; 2456 wait(); 2457 while(!RHC_OP_END.read()) { 2458 wait(); 2459 continue; 2460 } 2461 wait(); 2462 RHC_OP_START = 0; 2463 wait(); 2464 RHC_ADDR1 = 272; 2465 RHC_ADDR2 = (sig_gen_buff_addr, sc_int<7>(0)); 2466 RHC_OP_CODE = 1; 2467 EXC_RPBH_ID = id_reg; 2468 RHC_OP_START = 1; 2469 wait(); 2470 while(!RHC_OP_END.read()) { 2471 wait(); 2472 continue; 2473 } 2474 wait(); 2475 RHC_OP_START = 0; 2476 wait(); 2477 id_reg = -2; 2478 EXC_ADDR = -8192; 2479 EXC_RPBH_ID = id_reg; 2480 EXC_RW = 1; 2481 EXC_REQ = 1; 2482 wait(); 2483 while(1) { 2484 dtemp = IBC_DATA.read(); 2485 EXC_REQ = 0; 2486 if(IBC_GRANT_EXC) { 2487 wait(); 2488 break; 2489 } 2490 wait(); 2491 } 2492 sig_gen_buff_addr = dtemp.range(13,7); 2493 RHC_ADDR1 = (sig_gen_buff_addr, sc_int<7>(0)); 2494 RHC_ADDR2 = (sc_int<2>(0), total_data_len); 2495 RHC_SIZE = 22; 2496 RHC_OP_CODE = -3; 2497 RHC_OP_START = 1; 2498 wait(); 2499 while(!RHC_OP_END.read()) { 2500 wait(); 2501 continue; 2502 } 2503 wait(); 2504 RHC_OP_START = 0; 2505 wait(); 2506 RHC_ADDR1 = (RSN_reg, sc_int<6>(1)); 2507 RHC_ADDR2 = (sc_int<2>(0), total_data_len); 2508 RHC_SIZE = sig_gen_buff_addr; 2509 RHC_OP_CODE = -2; 2510 RHC_OP_START = 1; 2511 wait(); 2512 while(!RHC_OP_END.read()) { 2513 wait(); 2514 continue; 2515 } 2516 wait(); 2517 RHC_OP_START = 0; 2518 wait(); 2519 atemp = (sig_gen_buff_addr, sc_int<7>(10)); 2520 dt = 0; 2521 EXC_ADDR = atemp; 2522 EXC_DATA = dt; 2523 EXC_RW = 0; 2524 EXC_REQ = 1; 2525 wait(); 2526 while(1) { 2527 EXC_REQ = 0; 2528 if(IBC_GRANT_EXC) { 2529 wait(); 2530 break; 2531 } 2532 wait(); 2533 } 2534 RHC_ADDR1 = 16; 2535 RHC_ADDR2 = (sig_gen_buff_addr, sc_int<7>(24)); 2536 RHC_SIZE = 3; 2537 RHC_OP_CODE = 3; 2538 EXC_RPBH_ID = id_reg; 2539 RHC_OP_START = 1; 2540 wait(); 2541 while(!RHC_OP_END.read()) { 2542 wait(); 2543 continue; 2544 } 2545 wait(); 2546 RHC_OP_START = 0; 2547 wait(); 2548 RHC_ADDR1 = 96; 2549 RHC_ADDR2 = (sig_gen_buff_addr, sc_int<7>(27)); 2550 RHC_SIZE = 32; 2551 RHC_OP_CODE = 3; 2552 EXC_RPBH_ID = id_reg; 2553 RHC_OP_START = 1; 2554 wait(); 2555 while(!RHC_OP_END.read()) { 2556 wait(); 2557 continue; 2558 } 2559 wait(); 2560 RHC_OP_START = 0; 2561 wait(); 2562 RHC_ADDR1 = 160; 2563 RHC_ADDR2 = (sig_gen_buff_addr, sc_int<7>(59)); 2564 RHC_OP_CODE = 3; 2565 EXC_RPBH_ID = id_reg; 2566 RHC_OP_START = 1; 2567 wait(); 2568 while(!RHC_OP_END.read()) { 2569 wait(); 2570 continue; 2571 } 2572 wait(); 2573 RHC_OP_START = 0; 2574 wait(); 2575 RHC_ADDR1 = 48; 2576 RHC_ADDR2 = (sig_gen_buff_addr, sc_int<7>(-37)); 2577 RHC_SIZE = atemp_3.range(6,0); 2578 RHC_OP_CODE = 3; 2579 EXC_RPBH_ID = id_reg; 2580 RHC_OP_START = 1; 2581 wait(); 2582 while(!RHC_OP_END.read()) { 2583 wait(); 2584 continue; 2585 } 2586 wait(); 2587 RHC_OP_START = 0; 2588 wait(); 2589 RHC_ADDR1 = 4; 2590 RHC_ADDR2 = (sig_gen_buff_addr.range(6,0), atemp_1.range(6,0)); 2591 RHC_SIZE = 1; 2592 RHC_OP_CODE = 3; 2593 EXC_RPBH_ID = id_reg; 2594 RHC_OP_START = 1; 2595 wait(); 2596 while(!RHC_OP_END.read()) { 2597 wait(); 2598 continue; 2599 } 2600 wait(); 2601 RHC_OP_START = 0; 2602 wait(); 2603 RHC_ADDR1 = 20; 2604 RHC_ADDR2 = (sig_gen_buff_addr.range(6,0), atemp_2.range(6,0)); 2605 RHC_SIZE = 4; 2606 RHC_OP_CODE = 3; 2607 EXC_RPBH_ID = id_reg; 2608 RHC_OP_START = 1; 2609 wait(); 2610 while(!RHC_OP_END.read()) { 2611 wait(); 2612 continue; 2613 } 2614 wait(); 2615 RHC_OP_START = 0; 2616 wait(); 2617 RHC_ADDR1 = 288; 2618 RHC_ADDR2 = (sig_gen_buff_addr.range(6,0), sc_int<7>(0)); 2619 RHC_OP_CODE = 1; 2620 EXC_RPBH_ID = id_reg; 2621 RHC_OP_START = 1; 2622 wait(); 2623 while(!RHC_OP_END.read()) { 2624 wait(); 2625 continue; 2626 } 2627 wait(); 2628 RHC_OP_START = 0; 2629 wait(); 2630 } 2631 break; 2632 // } else if(10 == _case_1021_) { 2633 case 10: 2634 if(((MET_reg) != 3) || ((DID_reg) == 0)) { 2635 err_no_reg = 1; 2636 rb_flag = 1; 2637 wait(); 2638 } else { 2639 err_no_reg = err_no_reg; 2640 rb_flag = rb_flag; 2641 wait(); 2642 RHC_ADDR1 = (sig_gen_buff_addr, sc_int<7>(24)); 2643 if(DID_reg[0]) { 2644 atemp_1 = 128; 2645 atemp_2 = 32; 2646 atemp_3 = 2; 2647 atemp_4 = 272; 2648 atemp = 64; 2649 DID_reg = 10; 2650 RHC_ADDR2 = 8; 2651 } else { 2652 atemp_1 = 160; 2653 atemp_2 = 48; 2654 atemp_3 = 4; 2655 atemp_4 = 288; 2656 atemp = 96; 2657 DID_reg = 11; 2658 RHC_ADDR2 = 16; 2659 } 2660 RHC_SIZE = 3; 2661 RHC_OP_CODE = 3; 2662 EXC_RPBH_ID = id_reg; 2663 RHC_OP_START = 1; 2664 wait(); 2665 while(!RHC_OP_END.read()) { 2666 wait(); 2667 continue; 2668 } 2669 wait(); 2670 RHC_OP_START = 0; 2671 wait(); 2672 RHC_ADDR1 = (sig_gen_buff_addr, sc_int<7>(27)); 2673 RHC_ADDR2 = atemp; 2674 RHC_SIZE = 32; 2675 RHC_OP_CODE = 3; 2676 EXC_RPBH_ID = id_reg; 2677 RHC_OP_START = 1; 2678 wait(); 2679 while(!RHC_OP_END.read()) { 2680 wait(); 2681 continue; 2682 } 2683 wait(); 2684 RHC_OP_START = 0; 2685 wait(); 2686 RHC_ADDR1 = (sig_gen_buff_addr, sc_int<7>(59)); 2687 RHC_ADDR2 = atemp_1; 2688 RHC_OP_CODE = 3; 2689 EXC_RPBH_ID = id_reg; 2690 RHC_OP_START = 1; 2691 wait(); 2692 while(!RHC_OP_END.read()) { 2693 wait(); 2694 continue; 2695 } 2696 wait(); 2697 RHC_OP_START = 0; 2698 wait(); 2699 RHC_ADDR1 = (sig_gen_buff_addr, sc_int<7>(-37)); 2700 RHC_ADDR2 = atemp_2; 2701 if(!MODE_S_P.read()) { 2702 atemp_1 = -3743; 2703 RHC_SIZE = 6; 2704 } else { 2705 atemp_1 = -4001; 2706 RHC_SIZE = 4; 2707 } 2708 RHC_OP_CODE = 3; 2709 EXC_RPBH_ID = id_reg; 2710 RHC_OP_START = 1; 2711 wait(); 2712 while(!RHC_OP_END.read()) { 2713 wait(); 2714 continue; 2715 } 2716 wait(); 2717 RHC_OP_START = 0; 2718 wait(); 2719 RHC_ADDR1 = (sig_gen_buff_addr.range(6,0), atemp_1.range(6,0)); 2720 RHC_ADDR2 = atemp_3; 2721 RHC_SIZE = 1; 2722 RHC_OP_CODE = 3; 2723 EXC_RPBH_ID = id_reg; 2724 RHC_OP_START = 1; 2725 wait(); 2726 while(!RHC_OP_END.read()) { 2727 wait(); 2728 continue; 2729 } 2730 wait(); 2731 RHC_OP_START = 0; 2732 wait(); 2733 RHC_ADDR1 = (sig_gen_buff_addr.range(6,0), atemp_1.range(13,7)); 2734 RHC_ADDR2 = 20; 2735 RHC_SIZE = 4; 2736 RHC_OP_CODE = 3; 2737 EXC_RPBH_ID = id_reg; 2738 RHC_OP_START = 1; 2739 wait(); 2740 while(!RHC_OP_END.read()) { 2741 wait(); 2742 continue; 2743 } 2744 wait(); 2745 RHC_OP_START = 0; 2746 wait(); 2747 RHC_ADDR1 = (sig_gen_buff_addr, sc_int<7>(0)); 2748 RHC_ADDR2 = 0; 2749 RHC_SIZE = ((sc_int<1>(0), DID_reg), sc_int<1>(0)); 2750 RHC_OP_CODE = -3; 2751 RHC_OP_START = 1; 2752 wait(); 2753 while(!RHC_OP_END.read()) { 2754 wait(); 2755 continue; 2756 } 2757 wait(); 2758 RHC_OP_START = 0; 2759 wait(); 2760 RHC_ADDR1 = 768; 2761 RHC_ADDR2 = 0; 2762 RHC_SIZE = sig_gen_buff_addr; 2763 RHC_OP_CODE = -2; 2764 RHC_OP_START = 1; 2765 wait(); 2766 while(!RHC_OP_END.read()) { 2767 wait(); 2768 continue; 2769 } 2770 wait(); 2771 RHC_OP_START = 0; 2772 wait(); 2773 2774 //Write Buffer Queue 2775 RHC_ADDR1 = atemp_4; 2776 RHC_ADDR2 = (sig_gen_buff_addr, sc_int<7>(0)); 2777 2778 //Macro:write_queue(begin) 2779 RHC_OP_CODE = 1; 2780 EXC_RPBH_ID = id_reg; 2781 RHC_OP_START = 1; 2782 wait(); 2783 while(!RHC_OP_END.read()) { 2784 wait(); 2785 continue; 2786 } 2787 wait(); 2788 //Macro:write_queue(end) 2789 RHC_OP_START = 0; 2790 wait(); 2791 } 2792 break; 2793 // } else { 2794 default: 2795 err_no_reg = 3; 2796 rb_flag = 1; 2797 wait(); 2798 2799 } // end _case_1021_ 2800 2801 _signal_proc__END:; } while(0); 2802 if((err_no_reg) != 0) { 2803 error = err_no_reg; 2804 wait(); 2805 error = 0; 2806 wait(); 2807 } else { 2808 wait(); 2809 } 2810 if((rb_flag) != 0) { 2811 dt = ((sc_int<1>(0), sig_gen_buff_addr), sc_int<8>(0)); 2812 EXC_ADDR = -8192; 2813 EXC_DATA = dt; 2814 EXC_RW = 0; 2815 EXC_REQ = 1; 2816 wait(); 2817 while(1) { 2818 EXC_REQ = 0; 2819 if(IBC_GRANT_EXC) { 2820 wait(); 2821 break; 2822 } 2823 wait(); 2824 } 2825 } else { 2826 wait(); 2827 } 2828 } // end start 2829 } // end main 2830 } // main entry 2831 2832int 2833sc_main( int argc, char* argv[] ) 2834{ 2835 return 0; 2836} 2837