a2901_test.h revision 12855:588919e0e4aa 
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3  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
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6  Accellera licenses this file to you under the Apache License, Version 2.0
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10    http://www.apache.org/licenses/LICENSE-2.0
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12  Unless required by applicable law or agreed to in writing, software
13  distributed under the License is distributed on an "AS IS" BASIS,
14  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
15  implied.  See the License for the specific language governing
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19
20/*****************************************************************************
21
22  a2901_test.h --
23
24  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25
26 *****************************************************************************/
27
28/*****************************************************************************
29
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
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33      Name, Affiliation, Date:
34  Description of Modification:
35
36 *****************************************************************************/
37
38#ifndef A2901_TEST_H
39#define A2901_TEST_H
40
41#include "common.h"
42
43SC_MODULE( a2901_test )
44{
45    SC_HAS_PROCESS( a2901_test );
46
47    // clock
48    const sc_clock& CLK;
49
50    // inputs
51    const sig4& Y;
52    const sig1& t_RAM0;
53    const sig1& t_RAM3;
54    const sig1& t_Q0;
55    const sig1& t_Q3;
56    const sig1& C4;
57    const sig1& Gbar;
58    const sig1& Pbar;
59    const sig1& OVR;
60    const sig1& F3;
61    const sig1& F30;
62
63    // outputs
64    sig9& I;
65    sig4& Aadd;
66    sig4& Badd;
67    sig4& D;
68    sig1& RAM0;
69    sig1& RAM3;
70    sig1& Q0;
71    sig1& Q3;
72    sig1& C0;
73    sig1& OEbar;
74
75    // temporaries
76    int vec_cnt;
77    int loop;
78
79    // constructor
80    a2901_test( sc_module_name,
81                const sc_clock& CLK_,
82                const sig4& Y_,
83                const sig1& t_RAM0_,
84                const sig1& t_RAM3_,
85                const sig1& t_Q0_,
86                const sig1& t_Q3_,
87                const sig1& C4_,
88                const sig1& Gbar_,
89                const sig1& Pbar_,
90                const sig1& OVR_,
91                const sig1& F3_,
92                const sig1& F30_,
93                sig9&       I_,
94                sig4&       Aadd_,
95                sig4&       Badd_,
96                sig4&       D_,
97                sig1&       RAM0_,
98                sig1&       RAM3_,
99                sig1&       Q0_,
100                sig1&       Q3_,
101                sig1&       C0_,
102                sig1&       OEbar_ )
103    : CLK( CLK_ ),
104      Y( Y_ ),
105      t_RAM0( t_RAM0_ ),
106      t_RAM3( t_RAM3_ ),
107      t_Q0( t_Q0_ ),
108      t_Q3( t_Q3_ ),
109      C4( C4_ ),
110      Gbar( Gbar_ ),
111      Pbar( Pbar_ ),
112      OVR( OVR_ ),
113      F3( F3_ ),
114      F30( F30_ ),
115      I( I_ ),
116      Aadd( Aadd_ ),
117      Badd( Badd_ ),
118      D( D_ ),
119      RAM0( RAM0_ ),
120      RAM3( RAM3_ ),
121      Q0( Q0_ ),
122      Q3( Q3_ ),
123      C0( C0_ ),
124      OEbar( OEbar_ )
125    {
126        vec_cnt = 0;
127        loop = 0;
128
129        // init
130        I.write( 0x7 );
131        D.write( 0 );
132        C0.write( 0 );
133        OEbar.write( 0 );
134        Aadd.write( 0 );
135        Badd.write( 0 );
136        Q0.write( 0 );
137        Q3.write( 0 );
138
139        SC_METHOD( entry );
140        sensitive << CLK.posedge_event();
141    }
142
143    void entry();
144};
145
146#endif
147