tvec1.cpp revision 12855:588919e0e4aa
1/***************************************************************************** 2 3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 4 more contributor license agreements. See the NOTICE file distributed 5 with this work for additional information regarding copyright ownership. 6 Accellera licenses this file to you under the Apache License, Version 2.0 7 (the "License"); you may not use this file except in compliance with the 8 License. You may obtain a copy of the License at 9 10 http://www.apache.org/licenses/LICENSE-2.0 11 12 Unless required by applicable law or agreed to in writing, software 13 distributed under the License is distributed on an "AS IS" BASIS, 14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 15 implied. See the License for the specific language governing 16 permissions and limitations under the License. 17 18 *****************************************************************************/ 19 20/***************************************************************************** 21 22 tvec1.cpp -- 23 24 Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 25 26 *****************************************************************************/ 27 28/***************************************************************************** 29 30 MODIFICATION LOG - modifiers, enter your name, affiliation, date and 31 changes you are making here. 32 33 Name, Affiliation, Date: 34 Description of Modification: 35 36 *****************************************************************************/ 37 38#include "systemc.h" 39 40typedef sc_signal_rv<2> sc_signal_resolved_vector; 41 42SC_MODULE( proc1 ) 43{ 44 SC_HAS_PROCESS( proc1 ); 45 46 sc_signal_resolved_vector& out; 47 sc_in<bool> in; 48 49 proc1( sc_module_name n, 50 sc_signal_resolved_vector& OUT_, 51 sc_signal<bool>& IN_ ) 52 : out(OUT_) 53 { 54 in(IN_); 55 SC_METHOD( entry ); 56 sensitive << in; 57 } 58 59 void entry(); 60}; 61 62void 63proc1::entry() 64{ 65 sc_lv<2> a; 66 67 if ((bool) in == true) { 68 cout << "P1: Set to 1" << endl; 69 a[0] = a[1] = '1'; 70 out = a; 71 } 72 else { 73 cout << "P1: Set to Z" << endl; 74 a[0] = a[1] = 'Z'; 75 out = a; 76 } 77} 78 79 80SC_MODULE( proc2 ) 81{ 82 SC_HAS_PROCESS( proc2 ); 83 84 sc_signal_resolved_vector& out; 85 sc_in<bool> in; 86 87 proc2( sc_module_name n, 88 sc_signal_resolved_vector& OUT_, 89 sc_signal<bool>& IN_ ) 90 : out(OUT_) 91 { 92 in(IN_); 93 SC_METHOD( entry ); 94 sensitive << in; 95 } 96 97 void entry(); 98}; 99 100void 101proc2::entry() 102{ 103 sc_lv<2> a; 104 105 if ((bool) in == false) { 106 cout << "P2: Set to 0" << endl; 107 a[0] = a[1] = '0'; 108 out = a; 109 } 110 else { 111 cout << "P2: Set to Z" << endl; 112 a[0] = a[1] = 'Z'; 113 out = a; 114 } 115} 116 117SC_MODULE( proc3 ) 118{ 119 SC_HAS_PROCESS( proc3 ); 120 121 const sc_signal_resolved_vector& in; 122 123 proc3( sc_module_name n, 124 const sc_signal_resolved_vector& IN_ ) 125 : in(IN_) 126 { 127 SC_METHOD( entry ); 128 sensitive << in; 129 } 130 131 void entry() 132 { 133 sc_lv<2> v; 134 v = in; 135 cout << "Value on Bus = " << v.to_string().c_str() << endl; 136 } 137}; 138 139int sc_main(int ac, char *av[]) 140{ 141 sc_signal_resolved_vector Bus; 142 sc_signal<bool> clock; 143 144 proc1 P1("P1", Bus, clock); 145 proc2 P2("P2", Bus, clock); 146 proc3 P3("P3", Bus); 147 148 sc_start(1, SC_NS); 149 clock = 1; 150 sc_start(10, SC_NS); 151 for (int i = 0; i < 3; i++) { 152 clock = 0; 153 sc_start(10, SC_NS); 154 clock = 1; 155 sc_start(10, SC_NS); 156 } 157 return 0; 158} 159 160