stimulus.h revision 12855:588919e0e4aa
1/***************************************************************************** 2 3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 4 more contributor license agreements. See the NOTICE file distributed 5 with this work for additional information regarding copyright ownership. 6 Accellera licenses this file to you under the Apache License, Version 2.0 7 (the "License"); you may not use this file except in compliance with the 8 License. You may obtain a copy of the License at 9 10 http://www.apache.org/licenses/LICENSE-2.0 11 12 Unless required by applicable law or agreed to in writing, software 13 distributed under the License is distributed on an "AS IS" BASIS, 14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 15 implied. See the License for the specific language governing 16 permissions and limitations under the License. 17 18 *****************************************************************************/ 19 20/***************************************************************************** 21 22 stimulus.h -- 23 24 Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 25 26 *****************************************************************************/ 27 28/***************************************************************************** 29 30 MODIFICATION LOG - modifiers, enter your name, affiliation, date and 31 changes you are making here. 32 33 Name, Affiliation, Date: 34 Description of Modification: 35 36 *****************************************************************************/ 37 38 39#include "common.h" 40 41SC_MODULE( stimulus ) 42{ 43 SC_HAS_PROCESS( stimulus ); 44 45 sc_in_clk clk; 46 47 sc_signal<bool>& reset; 48 sc_signal_bool_vector8& out_value1; // Output port 49 sc_signal_bool_vector8& out_value2; // Output port 50 sc_signal<long>& out_value3; // Output port 51 sc_signal<int>& out_value4; // Output port 52 sc_signal<short>& out_value5; // Output port 53 sc_signal<char>& out_value6; // Output port 54 sc_signal<char>& out_value7; // Output port 55 sc_signal<bool>& out_value8 ; 56 sc_signal_bool_vector4& out_value9; // Output port 57 sc_signal_logic_vector4& out_value10; // Output port 58 sc_signal<bool>& out_valid; // Output port 59 const sc_signal<bool>& in_ack; 60 61 // 62 // Constructor 63 // 64 65 stimulus( 66 sc_module_name NAME, // reference name 67 sc_clock& CLK, // clock 68 sc_signal<bool>& RESET, 69 sc_signal_bool_vector8& OUT_VALUE1, 70 sc_signal_bool_vector8& OUT_VALUE2, 71 sc_signal<long>& OUT_VALUE3, 72 sc_signal<int>& OUT_VALUE4, 73 sc_signal<short>& OUT_VALUE5, 74 sc_signal<char>& OUT_VALUE6, 75 sc_signal<char>& OUT_VALUE7, 76 sc_signal<bool>& OUT_VALUE8, 77 sc_signal_bool_vector4& OUT_VALUE9, 78 sc_signal_logic_vector4& OUT_VALUE10, 79 sc_signal<bool>& OUT_VALID, 80 const sc_signal<bool>& IN_ACK 81 ) 82 : 83 reset (RESET), 84 out_value1 (OUT_VALUE1), 85 out_value2 (OUT_VALUE2), 86 out_value3 (OUT_VALUE3), 87 out_value4 (OUT_VALUE4), 88 out_value5 (OUT_VALUE5), 89 out_value6 (OUT_VALUE6), 90 out_value7 (OUT_VALUE7), 91 out_value8 (OUT_VALUE8), 92 out_value9 (OUT_VALUE9), 93 out_value10 (OUT_VALUE10), 94 out_valid (OUT_VALID), 95 in_ack (IN_ACK) 96 { 97 clk (CLK); 98 SC_CTHREAD( entry, clk.pos() ); 99 }; 100 void entry(); 101}; 102// EOF 103 104