display.h revision 12855:588919e0e4aa 
1/*****************************************************************************
2
3  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
4  more contributor license agreements.  See the NOTICE file distributed
5  with this work for additional information regarding copyright ownership.
6  Accellera licenses this file to you under the Apache License, Version 2.0
7  (the "License"); you may not use this file except in compliance with the
8  License.  You may obtain a copy of the License at
9
10    http://www.apache.org/licenses/LICENSE-2.0
11
12  Unless required by applicable law or agreed to in writing, software
13  distributed under the License is distributed on an "AS IS" BASIS,
14  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
15  implied.  See the License for the specific language governing
16  permissions and limitations under the License.
17
18 *****************************************************************************/
19
20/*****************************************************************************
21
22  display.h --
23
24  Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30
25
26 *****************************************************************************/
27
28/*****************************************************************************
29
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
32
33      Name, Affiliation, Date:
34  Description of Modification:
35
36 *****************************************************************************/
37
38
39#include "common.h"
40
41SC_MODULE( display )
42{
43    SC_HAS_PROCESS( display );
44
45    sc_in_clk clk;
46
47    const sc_signal_bool_vector8&      in_value1;     // Output  port
48    const sc_signal_bool_vector8&      in_value2;     // Output  port
49    const sc_signal<long>&             in_value3;                        // Output  port
50    const sc_signal<int>&              in_value4;                        // Output  port
51    const sc_signal<short>&            in_value5;                        // Output  port
52    const sc_signal<char>&             in_value6;                        // Output  port
53    const sc_signal<bool>&             in_value7;                        // Output  port
54    const sc_signal_bool_vector4&      in_value8;    // Output  port
55    const sc_signal_logic_vector4&     in_value9;    // Output  port
56    const sc_signal<bool>&             in_valid;                         // Output  port
57
58   //
59   // Constructor
60   //
61
62   display(
63               sc_module_name    NAME,      // reference name
64               sc_clock&      CLK,          // clock
65               const sc_signal_bool_vector8&     IN_VALUE1,
66               const sc_signal_bool_vector8&     IN_VALUE2,
67               const sc_signal<long>&            IN_VALUE3,
68               const sc_signal<int>&             IN_VALUE4,
69               const sc_signal<short>&           IN_VALUE5,
70               const sc_signal<char>&            IN_VALUE6,
71               const sc_signal<bool>&            IN_VALUE7,
72               const sc_signal_bool_vector4&     IN_VALUE8,
73               const sc_signal_logic_vector4&    IN_VALUE9,
74               const sc_signal<bool>&            IN_VALID
75           )
76           :
77             in_value1    (IN_VALUE1),
78             in_value2    (IN_VALUE2),
79             in_value3    (IN_VALUE3),
80             in_value4    (IN_VALUE4),
81             in_value5    (IN_VALUE5),
82             in_value6    (IN_VALUE6),
83             in_value7    (IN_VALUE7),
84             in_value8    (IN_VALUE8),
85             in_value9    (IN_VALUE9),
86             in_valid     (IN_VALID)
87     {
88       clk          (CLK);
89	   SC_CTHREAD( entry, clk.pos() );
90     };
91
92
93 void entry();
94};
95
96// EOF
97
98