sharing.h revision 12855:588919e0e4aa
1/***************************************************************************** 2 3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 4 more contributor license agreements. See the NOTICE file distributed 5 with this work for additional information regarding copyright ownership. 6 Accellera licenses this file to you under the Apache License, Version 2.0 7 (the "License"); you may not use this file except in compliance with the 8 License. You may obtain a copy of the License at 9 10 http://www.apache.org/licenses/LICENSE-2.0 11 12 Unless required by applicable law or agreed to in writing, software 13 distributed under the License is distributed on an "AS IS" BASIS, 14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 15 implied. See the License for the specific language governing 16 permissions and limitations under the License. 17 18 *****************************************************************************/ 19 20/***************************************************************************** 21 22 sharing.h -- 23 24 Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-14 25 26 *****************************************************************************/ 27 28/***************************************************************************** 29 30 MODIFICATION LOG - modifiers, enter your name, affiliation, date and 31 changes you are making here. 32 33 Name, Affiliation, Date: 34 Description of Modification: 35 36 *****************************************************************************/ 37 38 39#include "common.h" 40 41SC_MODULE( sharing ) 42{ 43 SC_HAS_PROCESS( sharing ); 44 45 sc_in_clk clk; 46 47 const sc_signal<bool>& reset ; 48 const sc_signal_bool_vector4& in_value1; // Input port 49 const sc_signal_bool_vector5& in_value2; // Input port 50 const sc_signal_bool_vector6& in_value3; // Input port 51 const sc_signal_bool_vector7& in_value4; // Input port 52 const sc_signal_bool_vector8& in_value5; // Input port 53 const sc_signal<bool>& in_valid; // Input port 54 sc_signal<bool>& out_ack; // Output port 55 sc_signal_bool_vector4& out_value1; // Output port 56 sc_signal_bool_vector5& out_value2; // Output port 57 sc_signal_bool_vector6& out_value3; // Output port 58 sc_signal_bool_vector7& out_value4; // Output port 59 sc_signal_bool_vector8& out_value5; // Output port 60 sc_signal<bool>& out_valid; // Output port 61 62 // 63 // Constructor 64 // 65 66 sharing ( 67 sc_module_name NAME, // referense name 68 sc_clock& CLK, // clock 69 const sc_signal<bool>& RESET, 70 const sc_signal_bool_vector4& IN_VALUE1, 71 const sc_signal_bool_vector5& IN_VALUE2, 72 const sc_signal_bool_vector6& IN_VALUE3, 73 const sc_signal_bool_vector7& IN_VALUE4, 74 const sc_signal_bool_vector8& IN_VALUE5, 75 const sc_signal<bool>& IN_VALID, // Input port 76 sc_signal<bool>& OUT_ACK, 77 sc_signal_bool_vector4& OUT_VALUE1, 78 sc_signal_bool_vector5& OUT_VALUE2, 79 sc_signal_bool_vector6& OUT_VALUE3, 80 sc_signal_bool_vector7& OUT_VALUE4, 81 sc_signal_bool_vector8& OUT_VALUE5, 82 sc_signal<bool>& OUT_VALID // Output port 83 ) 84 : 85 reset (RESET), 86 in_value1 (IN_VALUE1), 87 in_value2 (IN_VALUE2), 88 in_value3 (IN_VALUE3), 89 in_value4 (IN_VALUE4), 90 in_value5 (IN_VALUE5), 91 in_valid (IN_VALID), 92 out_ack (OUT_ACK), 93 out_value1 (OUT_VALUE1), 94 out_value2 (OUT_VALUE2), 95 out_value3 (OUT_VALUE3), 96 out_value4 (OUT_VALUE4), 97 out_value5 (OUT_VALUE5), 98 out_valid (OUT_VALID) 99 100 { 101 clk (CLK); 102 SC_CTHREAD( entry, clk.pos() ); 103 reset_signal_is(reset,true); 104 }; 105 106 // 107 108 void entry (); 109 110}; 111 112// EOF 113 114