bitwidth.h revision 12855:588919e0e4aa 
1/*****************************************************************************
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3  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
4  more contributor license agreements.  See the NOTICE file distributed
5  with this work for additional information regarding copyright ownership.
6  Accellera licenses this file to you under the Apache License, Version 2.0
7  (the "License"); you may not use this file except in compliance with the
8  License.  You may obtain a copy of the License at
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10    http://www.apache.org/licenses/LICENSE-2.0
11
12  Unless required by applicable law or agreed to in writing, software
13  distributed under the License is distributed on an "AS IS" BASIS,
14  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
15  implied.  See the License for the specific language governing
16  permissions and limitations under the License.
17
18 *****************************************************************************/
19
20/*****************************************************************************
21
22  bitwidth.h --
23
24  Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-14
25
26 *****************************************************************************/
27
28/*****************************************************************************
29
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
32
33      Name, Affiliation, Date:
34  Description of Modification:
35
36 *****************************************************************************/
37
38
39#include "common.h"
40
41SC_MODULE( bitwidth )
42{
43    SC_HAS_PROCESS( bitwidth );
44
45    sc_in_clk clk;
46
47    //====================================================================
48    // [C] Always Needed Member Function
49    //        --  constructor
50    //        --  entry
51    //====================================================================
52
53    const sc_signal<bool>&             reset ;
54    const sc_signal_bool_vector2&      in_value1;     // Input  port
55    const sc_signal_bool_vector4&      in_value2;     // Input  port
56    const sc_signal_bool_vector6&      in_value3;     // Input  port
57    const sc_signal_bool_vector8&      in_value4;     // Input  port
58    const sc_signal<bool>&             in_valid;      // Input  port
59    sc_signal_bool_vector2&            out_value1;    // Output port
60    sc_signal_bool_vector4&            out_value2;    // Output port
61    sc_signal_bool_vector6&            out_value3;    // Output port
62    sc_signal_bool_vector8&            out_value4;    // Output port
63    sc_signal<bool>&                   out_ack;       // Output port
64    sc_signal<bool>&                   out_valid;     // Output port
65
66
67    //
68    // Constructor
69    //
70
71    bitwidth (
72               sc_module_name   NAME,          // referense name
73               sc_clock&        CLK,           // clock
74        const  sc_signal<bool>& RESET,
75        const  sc_signal_bool_vector2&            IN_VALUE1,
76        const  sc_signal_bool_vector4&            IN_VALUE2,
77        const  sc_signal_bool_vector6&            IN_VALUE3,
78        const  sc_signal_bool_vector8&            IN_VALUE4,
79        const  sc_signal<bool>&                   IN_VALID,     // Input  port
80               sc_signal_bool_vector2&            OUT_VALUE1,
81               sc_signal_bool_vector4&            OUT_VALUE2,
82               sc_signal_bool_vector6&            OUT_VALUE3,
83               sc_signal_bool_vector8&            OUT_VALUE4,
84               sc_signal<bool>&                   OUT_ACK,
85               sc_signal<bool>&                   OUT_VALID    // Output port
86        )
87        :
88          reset        (RESET),
89          in_value1    (IN_VALUE1),
90          in_value2    (IN_VALUE2),
91          in_value3    (IN_VALUE3),
92          in_value4    (IN_VALUE4),
93          in_valid     (IN_VALID),
94          out_value1   (OUT_VALUE1),
95          out_value2   (OUT_VALUE2),
96          out_value3   (OUT_VALUE3),
97          out_value4   (OUT_VALUE4),
98          out_ack      (OUT_ACK),
99          out_valid    (OUT_VALID)
100
101    {
102      clk          (CLK);
103	  SC_CTHREAD( entry, clk.pos() );
104      reset_signal_is(reset,true);
105    };
106
107    //
108
109void entry ();
110
111};
112
113// EOF
114
115
116