display.h revision 12855
12SN/A/***************************************************************************** 21762SN/A 32SN/A Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 42SN/A more contributor license agreements. See the NOTICE file distributed 52SN/A with this work for additional information regarding copyright ownership. 62SN/A Accellera licenses this file to you under the Apache License, Version 2.0 72SN/A (the "License"); you may not use this file except in compliance with the 82SN/A License. You may obtain a copy of the License at 92SN/A 102SN/A http://www.apache.org/licenses/LICENSE-2.0 112SN/A 122SN/A Unless required by applicable law or agreed to in writing, software 132SN/A distributed under the License is distributed on an "AS IS" BASIS, 142SN/A WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 152SN/A implied. See the License for the specific language governing 162SN/A permissions and limitations under the License. 172SN/A 182SN/A *****************************************************************************/ 192SN/A 202SN/A/***************************************************************************** 212SN/A 222SN/A display.h -- 232SN/A 242SN/A Original Author: Rocco Jonack, Synopsys, Inc., 1999-05-13 252SN/A 262SN/A *****************************************************************************/ 272665SN/A 282665SN/A/***************************************************************************** 292665SN/A 302SN/A MODIFICATION LOG - modifiers, enter your name, affiliation, date and 312SN/A changes you are making here. 322SN/A 332SN/A Name, Affiliation, Date: 341298SN/A Description of Modification: 351298SN/A 361259SN/A *****************************************************************************/ 372SN/A 382SN/A 39146SN/A#include "common.h" 40146SN/A 417632SBrad.Beckmann@amd.comSC_MODULE( display ) 428232Snate@binkert.org{ 433348SN/A SC_HAS_PROCESS( display ); 448229Snate@binkert.org 453348SN/A sc_in_clk clk; 463348SN/A 4756SN/A const sc_signal<int>& in_data1; // Input port 48695SN/A const sc_signal_bool_vector4& in_data2; // Input port 492SN/A const sc_signal_bool_vector4& in_data3; // Input port 502SN/A const sc_signal_bool_vector8& in_data4; // Input port 512SN/A const sc_signal_bool_vector8& in_data5; // Input port 521298SN/A const sc_signal<bool>& in_valid; 531298SN/A 543187SN/A display( sc_module_name NAME, 553349SN/A sc_clock& CLK, 563187SN/A const sc_signal<int>& IN_DATA1, 574898SN/A const sc_signal_bool_vector4& IN_DATA2, 584898SN/A const sc_signal_bool_vector4& IN_DATA3, 594898SN/A const sc_signal_bool_vector8& IN_DATA4, 604898SN/A const sc_signal_bool_vector8& IN_DATA5, 614898SN/A const sc_signal<bool>& IN_VALID 624898SN/A ) 634898SN/A : 643187SN/A in_data1(IN_DATA1), 653187SN/A in_data2(IN_DATA2), 663187SN/A in_data3(IN_DATA3), 673187SN/A in_data4(IN_DATA4), 683349SN/A in_data5(IN_DATA5), 693187SN/A in_valid(IN_VALID) 704895SN/A { 714895SN/A clk(CLK); 724895SN/A SC_CTHREAD( entry, clk.pos() ); 737823Ssteve.reinhardt@amd.com } 743187SN/A 753187SN/A void entry(); 763187SN/A}; 773349SN/A 783187SN/A// EOF 793204SN/A