bitwidth.h revision 12855:588919e0e4aa
1/***************************************************************************** 2 3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 4 more contributor license agreements. See the NOTICE file distributed 5 with this work for additional information regarding copyright ownership. 6 Accellera licenses this file to you under the Apache License, Version 2.0 7 (the "License"); you may not use this file except in compliance with the 8 License. You may obtain a copy of the License at 9 10 http://www.apache.org/licenses/LICENSE-2.0 11 12 Unless required by applicable law or agreed to in writing, software 13 distributed under the License is distributed on an "AS IS" BASIS, 14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 15 implied. See the License for the specific language governing 16 permissions and limitations under the License. 17 18 *****************************************************************************/ 19 20/***************************************************************************** 21 22 bitwidth.h -- 23 24 Original Author: Rocco Jonack, Synopsys, Inc., 1999-08-02 25 26 *****************************************************************************/ 27 28/***************************************************************************** 29 30 MODIFICATION LOG - modifiers, enter your name, affiliation, date and 31 changes you are making here. 32 33 Name, Affiliation, Date: 34 Description of Modification: 35 36 *****************************************************************************/ 37 38#include "common.h" 39 40SC_MODULE( bitwidth ) 41{ 42 SC_HAS_PROCESS( bitwidth ); 43 44 sc_in_clk clk; 45 46 //==================================================================== 47 // [C] Always Needed Member Function 48 // -- constructor 49 // -- entry 50 //==================================================================== 51 52 const sc_signal<bool>& reset ; 53 const sc_signal_bool_vector4& in_value1; // Input port 54 const sc_signal_bool_vector4& in_value2; // Input port 55 const sc_signal_bool_vector6& in_value3; // Input port 56 const sc_signal_bool_vector6& in_value4; // Input port 57 const sc_signal_bool_vector8& in_value5; // Input port 58 const sc_signal_bool_vector8& in_value6; // Input port 59 const sc_signal<bool>& in_valid; // Input port 60 sc_signal_bool_vector4& out_value1; // Output port 61 sc_signal_bool_vector4& out_value2; // Output port 62 sc_signal_bool_vector6& out_value3; // Output port 63 sc_signal_bool_vector6& out_value4; // Output port 64 sc_signal_bool_vector8& out_value5; // Output port 65 sc_signal_bool_vector8& out_value6; // Output port 66 sc_signal<bool>& out_valid; // Output port 67 68 // 69 // Constructor 70 // 71 72 bitwidth ( 73 sc_module_name NAME, // referense name 74 sc_clock& CLK, // clock 75 const sc_signal<bool>& RESET, 76 const sc_signal_bool_vector4& IN_VALUE1, 77 const sc_signal_bool_vector4& IN_VALUE2, 78 const sc_signal_bool_vector6& IN_VALUE3, 79 const sc_signal_bool_vector6& IN_VALUE4, 80 const sc_signal_bool_vector8& IN_VALUE5, 81 const sc_signal_bool_vector8& IN_VALUE6, 82 const sc_signal<bool>& IN_VALID, // Input port 83 sc_signal_bool_vector4& OUT_VALUE1, 84 sc_signal_bool_vector4& OUT_VALUE2, 85 sc_signal_bool_vector6& OUT_VALUE3, 86 sc_signal_bool_vector6& OUT_VALUE4, 87 sc_signal_bool_vector8& OUT_VALUE5, 88 sc_signal_bool_vector8& OUT_VALUE6, 89 sc_signal<bool>& OUT_VALID // Output port 90 ) 91 : 92 reset (RESET), 93 in_value1 (IN_VALUE1), 94 in_value2 (IN_VALUE2), 95 in_value3 (IN_VALUE3), 96 in_value4 (IN_VALUE4), 97 in_value5 (IN_VALUE5), 98 in_value6 (IN_VALUE6), 99 in_valid (IN_VALID), 100 out_value1 (OUT_VALUE1), 101 out_value2 (OUT_VALUE2), 102 out_value3 (OUT_VALUE3), 103 out_value4 (OUT_VALUE4), 104 out_value5 (OUT_VALUE5), 105 out_value6 (OUT_VALUE6), 106 out_valid (OUT_VALID) 107 108 { 109 clk (CLK); 110 SC_CTHREAD( entry, clk.pos() ); 111 reset_signal_is(reset,true); 112 }; 113 114 // 115 116 void entry (); 117 118}; 119 120// EOF 121