addition.h revision 12855:588919e0e4aa 
1/*****************************************************************************
2
3  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
4  more contributor license agreements.  See the NOTICE file distributed
5  with this work for additional information regarding copyright ownership.
6  Accellera licenses this file to you under the Apache License, Version 2.0
7  (the "License"); you may not use this file except in compliance with the
8  License.  You may obtain a copy of the License at
9
10    http://www.apache.org/licenses/LICENSE-2.0
11
12  Unless required by applicable law or agreed to in writing, software
13  distributed under the License is distributed on an "AS IS" BASIS,
14  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
15  implied.  See the License for the specific language governing
16  permissions and limitations under the License.
17
18 *****************************************************************************/
19
20/*****************************************************************************
21
22  addition.h --
23
24  Original Author: Rocco Jonack, Synopsys, Inc., 1999-05-12
25
26 *****************************************************************************/
27
28/*****************************************************************************
29
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
32
33      Name, Affiliation, Date:
34  Description of Modification:
35
36 *****************************************************************************/
37
38#include "common.h"
39
40SC_MODULE( addition )
41{
42    SC_HAS_PROCESS( addition );
43
44    sc_in_clk clk;
45
46    //====================================================================
47    // [C] Always Needed Member Function
48    //        --  constructor
49    //        --  entry
50    //====================================================================
51
52    const sc_signal<bool>&             reset ;
53    const sc_signal<int>&              in_value1;
54    const sc_signal_bool_vector4&      in_value2;
55    const sc_signal_bool_vector4&      in_value3;
56    const sc_signal_bool_vector8&      in_value4;
57    const sc_signal_bool_vector8&      in_value5;
58    const sc_signal<bool>&             in_valid;      // Input  port
59    sc_signal<int>&                    out_value1;    // Output port
60    sc_signal_bool_vector4&            out_value2;
61    sc_signal_bool_vector4&            out_value3;
62    sc_signal_bool_vector8&            out_value4;
63    sc_signal_bool_vector8&            out_value5;
64    sc_signal<bool>&                   out_valid;
65
66    //
67    // Constructor
68    //
69
70    addition(
71               sc_module_name   NAME, // reference name
72               sc_clock&        CLK,  // clock
73	const  sc_signal<bool>& RESET,
74        const  sc_signal<int>&                    IN_VALUE1,
75        const  sc_signal_bool_vector4&            IN_VALUE2,
76        const  sc_signal_bool_vector4&            IN_VALUE3,
77        const  sc_signal_bool_vector8&            IN_VALUE4,
78        const  sc_signal_bool_vector8&            IN_VALUE5,
79        const  sc_signal<bool>&                   IN_VALID,     // Input  port
80               sc_signal<int>&                    OUT_VALUE1,
81               sc_signal_bool_vector4&            OUT_VALUE2,
82               sc_signal_bool_vector4&            OUT_VALUE3,
83               sc_signal_bool_vector8&            OUT_VALUE4,
84               sc_signal_bool_vector8&            OUT_VALUE5,
85               sc_signal<bool>&                   OUT_VALID    // Output port
86        )
87        :
88          reset        (RESET), // connection definition
89	  in_value1    (IN_VALUE1),
90	  in_value2    (IN_VALUE2),
91	  in_value3    (IN_VALUE3),
92	  in_value4    (IN_VALUE4),
93	  in_value5    (IN_VALUE5),
94	  in_valid     (IN_VALID),
95          out_value1   (OUT_VALUE1),
96          out_value2   (OUT_VALUE2),
97          out_value3   (OUT_VALUE3),
98          out_value4   (OUT_VALUE4),
99          out_value5   (OUT_VALUE5),
100          out_valid    (OUT_VALID)
101
102    {
103	  clk(CLK);
104      SC_CTHREAD( entry, clk.pos() );
105	  reset_signal_is(reset,true);
106    };
107
108    //
109
110    void entry ();
111
112};
113
114// EOF
115