test05.log revision 12855:588919e0e4aa 
1SystemC Simulation
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6500 ps
7***
8sc_module  a
9sc_module  b
10sc_clock  clock_0
11sc_signal  signal_0
12sc_module  c
13sc_method_process  clock_0_posedge_action_0
14sc_method_process  clock_0_negedge_action_0
15***
16sc_in  a.port_0
17sc_out  a.port_1
18sc_method_process  a.main_action
19***
20sc_in  b.port_0
21sc_thread_process  b.main_action
22***
23sc_in  c.port_0
24sc_module  c.a
25sc_module  c.b
26sc_signal  c.signal_0
27sc_cthread_process  c.main_action
28***
29sc_in  c.a.port_0
30sc_out  c.a.port_1
31sc_method_process  c.a.main_action
32***
33sc_in  c.b.port_0
34sc_thread_process  c.b.main_action
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