test02.cpp revision 12855:588919e0e4aa
1/***************************************************************************** 2 3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 4 more contributor license agreements. See the NOTICE file distributed 5 with this work for additional information regarding copyright ownership. 6 Accellera licenses this file to you under the Apache License, Version 2.0 7 (the "License"); you may not use this file except in compliance with the 8 License. You may obtain a copy of the License at 9 10 http://www.apache.org/licenses/LICENSE-2.0 11 12 Unless required by applicable law or agreed to in writing, software 13 distributed under the License is distributed on an "AS IS" BASIS, 14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 15 implied. See the License for the specific language governing 16 permissions and limitations under the License. 17 18 *****************************************************************************/ 19 20/***************************************************************************** 21 22 test02.cpp -- 23 24 Original Author: Ucar Aziz, Synopsys, Inc., 2002-02-15 25 Martin Janssen, Synopsys, Inc., 2002-02-15 26 27 *****************************************************************************/ 28 29/***************************************************************************** 30 31 MODIFICATION LOG - modifiers, enter your name, affiliation, date and 32 changes you are making here. 33 34 Name, Affiliation, Date: 35 Description of Modification: 36 37 *****************************************************************************/ 38 39// test of sc_inout_resolved::operator= 40 41#include "systemc.h" 42 43 44SC_MODULE( mod_a) 45{ 46 sc_inout_resolved in_out1; 47 sc_inout_resolved in_out2; 48 sc_inout_resolved in_out3; 49 sc_inout_resolved in_out4; 50 sc_port<sc_signal_inout_if<sc_logic>,1> in_out5; 51 sc_port<sc_signal_in_if<sc_logic>,1> in_1; 52 53 sc_in<bool> clk; 54 55 void main_action() 56 { 57 58 sc_logic m; 59 m = 'Z'; 60 61 while(1){ 62 wait(); 63 cout<< m<<" "; 64 in_out1 = m; 65 cout<<in_out1->read()<<" "; 66 in_out2 = in_out1; 67 cout<<in_out2->read()<<" "; 68 in_out3 = in_1; 69 cout<<in_out3->read()<<" "; 70 in_out4 = in_out5; 71 cout<<in_out4->read()<<endl; 72 } 73 } 74 75 SC_CTOR( mod_a ) 76 { 77 SC_THREAD(main_action) 78 sensitive << clk.pos(); 79 } 80}; 81 82int sc_main(int, char*[]) 83{ 84 sc_clock clk("clk", 5, SC_NS); 85 mod_a a("a"); 86 sc_signal_resolved sig1; 87 sc_signal_resolved sig2; 88 sc_signal_resolved sig3; 89 sc_signal<sc_logic> sig4; 90 sc_signal_resolved sig5; 91 sc_signal<sc_logic> sig6; 92 93 a.clk(clk); 94 a.in_out1(sig1); 95 a.in_out2(sig2); 96 a.in_out3(sig3); 97 a.in_1(sig4); 98 a.in_out4(sig5); 99 a.in_out5(sig6); 100 101 sc_start(15, SC_NS); 102 return 0; 103} 104