test01.cpp revision 12855:588919e0e4aa
1/***************************************************************************** 2 3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 4 more contributor license agreements. See the NOTICE file distributed 5 with this work for additional information regarding copyright ownership. 6 Accellera licenses this file to you under the Apache License, Version 2.0 7 (the "License"); you may not use this file except in compliance with the 8 License. You may obtain a copy of the License at 9 10 http://www.apache.org/licenses/LICENSE-2.0 11 12 Unless required by applicable law or agreed to in writing, software 13 distributed under the License is distributed on an "AS IS" BASIS, 14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 15 implied. See the License for the specific language governing 16 permissions and limitations under the License. 17 18 *****************************************************************************/ 19 20/***************************************************************************** 21 22 test01.cpp -- 23 24 Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 25 26 *****************************************************************************/ 27 28/***************************************************************************** 29 30 MODIFICATION LOG - modifiers, enter your name, affiliation, date and 31 changes you are making here. 32 33 Name, Affiliation, Date: 34 Description of Modification: 35 36 *****************************************************************************/ 37 38// test of sc_signal_resolved 39 40#include "systemc.h" 41 42SC_MODULE( mod_a ) 43{ 44 // ports 45 sc_out_resolved out1; 46 sc_out_resolved out2; 47 sc_in_resolved in; 48 49 // variables 50 sc_logic l1; 51 sc_logic l2; 52 53 // events 54 sc_event ready1; 55 sc_event ready2; 56 57 void out_action1() 58 { 59 for( int i = 0; i < 4; ++ i ) { 60 l1 = sc_dt::sc_logic_value_t( i ); 61 for( int j = 0; j < 4; ++j ) { 62 out1.write( l1 ); 63 wait( 1, SC_NS ); 64 ready1.notify(); 65 wait( SC_ZERO_TIME ); 66 } 67 } 68 } 69 70 void out_action2() 71 { 72 for( int i = 0; i < 4; ++ i ) { 73 for( int j = 0; j < 4; ++ j ) { 74 l2 = sc_dt::sc_logic_value_t( j ); 75 out2.write( l2 ); 76 wait( 1, SC_NS ); 77 ready2.notify(); 78 wait( SC_ZERO_TIME ); 79 } 80 } 81 } 82 83 void in_action() 84 { 85 for( int i = 0; i < 16; ++ i ) { 86 wait( ready1 & ready2 ); 87 cout << l1 << " " << l2 << " -> " << in.read() << endl; 88 } 89 } 90 91 SC_CTOR( mod_a ) 92 { 93 SC_THREAD( out_action1 ); 94 SC_THREAD( out_action2 ); 95 SC_THREAD( in_action ); 96 } 97}; 98 99int 100sc_main( int, char*[] ) 101{ 102 sc_signal_resolved sig; 103 104 mod_a a( "a" ); 105 106 a.out1( sig ); 107 a.out2( sig ); 108 a.in( sig ); 109 110 sc_start(); 111 112 return 0; 113} 114