test02.cpp revision 12855:588919e0e4aa 
1/*****************************************************************************
2
3  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
4  more contributor license agreements.  See the NOTICE file distributed
5  with this work for additional information regarding copyright ownership.
6  Accellera licenses this file to you under the Apache License, Version 2.0
7  (the "License"); you may not use this file except in compliance with the
8  License.  You may obtain a copy of the License at
9
10    http://www.apache.org/licenses/LICENSE-2.0
11
12  Unless required by applicable law or agreed to in writing, software
13  distributed under the License is distributed on an "AS IS" BASIS,
14  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
15  implied.  See the License for the specific language governing
16  permissions and limitations under the License.
17
18 *****************************************************************************/
19
20/*****************************************************************************
21
22  test02.cpp --
23
24  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25
26 *****************************************************************************/
27
28/*****************************************************************************
29
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
32
33      Name, Affiliation, Date:
34  Description of Modification:
35
36 *****************************************************************************/
37
38// test of signal port event methods
39
40#include "systemc.h"
41
42SC_MODULE( mod_a )
43{
44    sc_in<int>         in_int;
45    sc_in<bool>        in_bool;
46    sc_in<sc_logic>    in_logic;
47
48    void main_action()
49    {
50        wait( in_int.default_event() );
51        cout << "in_int       default_event()" << endl;
52        wait( in_int.value_changed_event() );
53        cout << "in_int       value_changed_event()" << endl;
54
55        wait( in_bool.default_event() );
56        cout << "in_bool      default_event()" << endl;
57        wait( in_bool.value_changed_event() );
58        cout << "in_bool      value_changed_event()" << endl;
59        wait( in_bool.posedge_event() );
60        cout << "in_bool      posedge_event()" << endl;
61        wait( in_bool.negedge_event() );
62        cout << "in_bool      negedge_event()" << endl;
63
64        wait( in_logic.default_event() );
65        cout << "in_logic     default_event()" << endl;
66        wait( in_logic.value_changed_event() );
67        cout << "in_logic     value_changed_event()" << endl;
68        wait( in_logic.posedge_event() );
69        cout << "in_logic     posedge_event()" << endl;
70        wait( in_logic.negedge_event() );
71        cout << "in_logic     negedge_event()" << endl;
72
73        sc_stop();
74    }
75
76    SC_CTOR( mod_a )
77    {
78        SC_THREAD( main_action );
79    }
80};
81
82SC_MODULE( mod_b )
83{
84    sc_in_clk clk;
85
86    sc_out<bool>     out_bool;
87    sc_out<int>      out_int;
88    sc_out<sc_logic> out_logic;
89
90    void main_action()
91    {
92        int i = 0;
93        bool b = false;
94        sc_logic l = SC_LOGIC_0;
95        while( true ) {
96            wait();
97            out_int.write( i );
98            i ++;
99            out_bool.write( b );
100            b = !b;
101            out_logic.write( l );
102            l = ~l;
103        }
104    }
105
106    SC_CTOR( mod_b )
107    {
108        SC_THREAD( main_action );
109        sensitive << clk.pos();
110    }
111};
112
113int
114sc_main( int, char*[] )
115{
116    sc_clock clk( "clk", 10, SC_NS );
117
118    mod_a a( "a" );
119    mod_b b( "b" );
120
121    sc_signal<int> sig_int;
122    sc_signal<bool> sig_bool;
123    sc_signal<sc_logic> sig_logic;
124
125    b.clk( clk );
126    b.out_bool( sig_bool );
127    b.out_int( sig_int );
128    b.out_logic( sig_logic );
129
130    a.in_int( sig_int );
131    a.in_bool( sig_bool );
132    a.in_logic( sig_logic );
133
134    sc_start();
135
136    return 0;
137}
138