test07.cpp revision 12855:588919e0e4aa
1/*****************************************************************************
2
3  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
4  more contributor license agreements.  See the NOTICE file distributed
5  with this work for additional information regarding copyright ownership.
6  Accellera licenses this file to you under the Apache License, Version 2.0
7  (the "License"); you may not use this file except in compliance with the
8  License.  You may obtain a copy of the License at
9
10    http://www.apache.org/licenses/LICENSE-2.0
11
12  Unless required by applicable law or agreed to in writing, software
13  distributed under the License is distributed on an "AS IS" BASIS,
14  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
15  implied.  See the License for the specific language governing
16  permissions and limitations under the License.
17
18 *****************************************************************************/
19
20/*****************************************************************************
21
22  test07.cpp --
23
24  Original Author: Ucar Aziz, Synopsys, Inc., 2002-02-15
25                   Martin Janssen, Synopsys, Inc., 2002-02-15
26
27 *****************************************************************************/
28
29/*****************************************************************************
30
31  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
32  changes you are making here.
33
34      Name, Affiliation, Date:
35  Description of Modification:
36
37 *****************************************************************************/
38
39// test of sc_prim_channel::next_trigger(const sc_time&, sc_event&)
40
41#include <systemc.h>
42
43//write and read interfaces
44class write_if : virtual public
45sc_interface
46 {
47  public:
48   virtual void write() = 0;
49};
50
51class read_if : virtual public
52sc_interface
53{
54 public:
55  virtual void read( ) = 0;
56};
57
58// channel implements write_if and read_if interfaces
59class channel :
60  public sc_channel,
61  public write_if,
62  public read_if
63{
64
65  public :
66
67  //constructor
68  channel(sc_module_name name):sc_channel(name)  , data(0)
69  { }
70
71  //write to channel
72  void write(){
73    static int i = 0;
74    next_trigger(10, SC_NS);
75    data = i;
76    cout <<"simulation time" << ":" << sc_time_stamp()<<"    ";
77    cout<<"writting "<< data <<" to channel" << endl;
78
79    if(i < 5){
80      write_event.notify(20, SC_NS);
81    }
82    else {
83      write_event.notify(5, SC_NS);
84	}
85
86    i++;
87  }
88
89  //read from channel
90  void read( ){
91    int j;
92    const sc_time t(10, SC_NS);
93    next_trigger(t, write_event);
94    j = data;
95    cout <<"simulation time" << ":" << sc_time_stamp();
96    cout<<"    reading "<<j<<" from channel" << endl;
97  }
98
99  private:
100  int data;
101  sc_event write_event;
102
103};
104
105//source module
106SC_MODULE(mod_a)
107{
108  sc_port<write_if> out;
109
110  void write( )
111  {
112    out->write();
113  }
114
115  SC_CTOR( mod_a ){
116
117    SC_METHOD(write);
118  }
119};
120
121//sink module
122SC_MODULE(mod_b)
123{
124  sc_port<read_if> input;
125  int i;
126
127  void read( )
128  {
129   input->read();
130  }
131
132  SC_CTOR( mod_b ){
133
134    SC_METHOD(read);
135  }
136};
137
138
139int sc_main(int, char*[] )
140{
141  channel a("a");
142  mod_a modul_a("modul_a");
143  mod_b modul_b("modul_b");
144  modul_a.out(a);
145  modul_b.input(a);
146
147  sc_start(100, SC_NS);
148  return 0 ;
149}
150