test01.cpp revision 12855:588919e0e4aa
1/***************************************************************************** 2 3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 4 more contributor license agreements. See the NOTICE file distributed 5 with this work for additional information regarding copyright ownership. 6 Accellera licenses this file to you under the Apache License, Version 2.0 7 (the "License"); you may not use this file except in compliance with the 8 License. You may obtain a copy of the License at 9 10 http://www.apache.org/licenses/LICENSE-2.0 11 12 Unless required by applicable law or agreed to in writing, software 13 distributed under the License is distributed on an "AS IS" BASIS, 14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 15 implied. See the License for the specific language governing 16 permissions and limitations under the License. 17 18 *****************************************************************************/ 19 20/***************************************************************************** 21 22 test01.cpp -- 23 24 Original Author: Ucar Aziz, Synopsys, Inc., 2002-02-15 25 Martin Janssen, Synopsys, Inc., 2002-02-15 26 27 *****************************************************************************/ 28 29/***************************************************************************** 30 31 MODIFICATION LOG - modifiers, enter your name, affiliation, date and 32 changes you are making here. 33 34 Name, Affiliation, Date: 35 Description of Modification: 36 37 *****************************************************************************/ 38 39//test of sc_prim_channel::next_trigger() 40 41#include <systemc.h> 42 43//write and read interfaces 44class write_if : virtual public 45sc_interface 46 { 47 public: 48 virtual void write() = 0; 49}; 50 51class read_if : virtual public 52sc_interface 53{ 54 public: 55 virtual void read( ) = 0; 56}; 57 58// channel implements write_if and read_if interfaces 59class channel : 60 public sc_channel, 61 public write_if, 62 public read_if 63{ 64 65 public : 66 67 //constructor 68 channel(sc_module_name name):sc_channel(name), data(0) 69 { } 70 71 //write to channel 72 void write(){ 73 static int i = 0; 74 next_trigger(); 75 data = i; 76 cout <<"simulation time" << ":" << sc_time_stamp()<<" "; 77 cout<<"writting "<< data <<" to channel" << endl; 78 i++; 79 } 80 81 //read from channel 82 void read( ){ 83 int j; 84 next_trigger(); 85 j = data; 86 cout <<"simulation time" << ":" << sc_time_stamp(); 87 cout<<" reading "<<j<<" from channel" << endl; 88 } 89 90 private: 91 int data; 92 93}; 94 95//source module 96SC_MODULE(mod_a) 97{ 98 sc_port<write_if> out; 99 100 void write( ) 101 { 102 out->write(); 103 } 104 105 SC_CTOR( mod_a ){ 106 107 SC_METHOD(write); 108 } 109}; 110 111//sink module 112SC_MODULE(mod_b) 113{ 114 sc_port<read_if> input; 115 int i; 116 117 void read( ) 118 { 119 input->read(); 120 } 121 122 SC_CTOR( mod_b ){ 123 124 SC_METHOD(read); 125 } 126}; 127 128 129int sc_main(int, char*[] ) 130{ 131 channel a("a"); 132 mod_a modul_a("modul_a"); 133 mod_b modul_b("modul_b"); 134 modul_a.out(a); 135 modul_b.input(a); 136 137 sc_start(10, SC_NS); 138 return 0 ; 139} 140