test04.cpp revision 12855:588919e0e4aa 
1/*****************************************************************************
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3  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
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5  with this work for additional information regarding copyright ownership.
6  Accellera licenses this file to you under the Apache License, Version 2.0
7  (the "License"); you may not use this file except in compliance with the
8  License.  You may obtain a copy of the License at
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10    http://www.apache.org/licenses/LICENSE-2.0
11
12  Unless required by applicable law or agreed to in writing, software
13  distributed under the License is distributed on an "AS IS" BASIS,
14  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
15  implied.  See the License for the specific language governing
16  permissions and limitations under the License.
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18 *****************************************************************************/
19
20/*****************************************************************************
21
22  test04.cpp --
23
24  Original Author: Ucar Aziz, Synopsys, Inc., 2002-02-15
25                   Martin Janssen, Synopsys, Inc., 2002-02-15
26
27 *****************************************************************************/
28
29/*****************************************************************************
30
31  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
32  changes you are making here.
33
34      Name, Affiliation, Date:
35  Description of Modification:
36
37 *****************************************************************************/
38
39//test of port connections
40
41#include "systemc.h"
42
43
44#define WRITE(a) \
45    cout << a.name() << " (" << a.kind() << ")" << endl
46
47
48SC_MODULE( mod_a)
49{
50  sc_port<sc_signal_in_if<bool>,2> in_1;
51  sc_port<sc_signal_in_if<sc_logic>,2> in_2;
52  sc_port<sc_signal_inout_if<bool>,2> inout_1;
53  sc_port<sc_signal_inout_if<sc_logic>,2> inout_2;
54
55  SC_CTOR( mod_a )
56    {
57     WRITE(in_1);
58     WRITE(in_2);
59     WRITE(inout_1);
60     WRITE(inout_2);
61    }
62};
63
64SC_MODULE( mod_b)
65{
66  sc_port<sc_signal_in_if<bool>,2> in_1;
67  sc_port<sc_signal_in_if<sc_logic>,2> in_2;
68  sc_port<sc_signal_inout_if<bool>,2> inout_1;
69  sc_port<sc_signal_inout_if<sc_logic>,2> inout_2;
70
71  SC_CTOR( mod_b )
72    {
73     WRITE(in_1);
74     WRITE(in_2);
75     WRITE(inout_1);
76     WRITE(inout_2);
77    }
78};
79
80SC_MODULE( mod_c )
81{
82  sc_port<sc_signal_in_if<bool>,0> input_1;
83  sc_port<sc_signal_in_if<bool>,3> input_2;
84  sc_port<sc_signal_in_if<sc_logic>,0> input_3;
85  sc_port<sc_signal_in_if<sc_logic>,3> input_4;
86  sc_port<sc_signal_inout_if<bool>,0> inout_1;
87  sc_port<sc_signal_inout_if<bool>,3> inout_2;
88  sc_port<sc_signal_inout_if<sc_logic>,0> inout_3;
89  sc_port<sc_signal_inout_if<sc_logic>,3> inout_4;
90  sc_signal<bool> sig_1;
91  sc_signal<bool> sig_2;
92  sc_signal<sc_logic> sig_3;
93  sc_signal<sc_logic> sig_4;
94
95  mod_a a;
96  mod_b b;
97
98  SC_CTOR( mod_c )
99    :a("a"), b("b")
100  {
101    a.in_1(input_2);
102    a.in_1(sig_1);
103    a.in_2(input_4);
104    a.in_2(sig_3);
105    a.inout_1(inout_2);
106    a.inout_1(sig_2);
107    a.inout_2(inout_4);
108    a.inout_2(sig_4);
109
110    b.in_1(input_1);
111    b.in_1(input_2);
112    b.in_2(input_3);
113    b.in_2(input_4);
114    b.inout_1(inout_1);
115    b.inout_1(inout_2);
116    b.inout_2(inout_3);
117    b.inout_2(inout_4);
118
119     WRITE(input_1);
120     WRITE(input_2);
121     WRITE(inout_1);
122     WRITE(inout_2);
123 }
124};
125
126SC_MODULE( mod_d )
127{
128  sc_port<sc_signal_in_if<bool>,1> input_1;
129  sc_port<sc_signal_in_if<sc_logic>,1> input_2;
130  sc_port<sc_signal_inout_if<bool>,1> inout_1;
131  sc_port<sc_signal_inout_if<sc_logic>,1> inout_2;
132
133  mod_c c;
134
135  SC_CTOR( mod_d )
136    : input_1("input_1"), input_2("input_2"),
137    inout_1("inout_1"), inout_2("inout_2"), c("c")
138  {
139    c.input_1(input_1);
140    c.input_3(input_2);
141    c.inout_1(inout_1);
142    c.inout_3(inout_2);
143  }
144};
145
146
147int sc_main(int, char* []){
148
149  mod_d d("d");
150
151  return 0;
152}
153