test02.cpp revision 12855:588919e0e4aa
1/***************************************************************************** 2 3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 4 more contributor license agreements. See the NOTICE file distributed 5 with this work for additional information regarding copyright ownership. 6 Accellera licenses this file to you under the Apache License, Version 2.0 7 (the "License"); you may not use this file except in compliance with the 8 License. You may obtain a copy of the License at 9 10 http://www.apache.org/licenses/LICENSE-2.0 11 12 Unless required by applicable law or agreed to in writing, software 13 distributed under the License is distributed on an "AS IS" BASIS, 14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 15 implied. See the License for the specific language governing 16 permissions and limitations under the License. 17 18 *****************************************************************************/ 19 20/***************************************************************************** 21 22 test02.cpp -- 23 24 Original Author: Ucar Aziz, Synopsys, Inc., 2002-02-15 25 Martin Janssen, Synopsys, Inc., 2002-02-15 26 27 *****************************************************************************/ 28 29/***************************************************************************** 30 31 MODIFICATION LOG - modifiers, enter your name, affiliation, date and 32 changes you are making here. 33 34 Name, Affiliation, Date: 35 Description of Modification: 36 37 *****************************************************************************/ 38 39// test of ports binding in hierarchical model 40 41#include "systemc.h" 42 43SC_MODULE( mod_a ) 44{ 45 46 sc_in<int> in; 47 sc_out<int> out; 48 49 SC_CTOR( mod_a ) 50 { } 51}; 52 53SC_MODULE( mod_b ) 54{ 55 56 sc_in<int> in; 57 sc_out<int> out; 58 59 SC_CTOR( mod_b ) 60 { } 61}; 62 63// parent model 64SC_MODULE( mod_c ) 65{ 66 67 sc_in<int> input; 68 sc_out<int> output; 69 sc_signal<int> buf; 70 mod_a module_a; 71 mod_b module_b; 72 73 SC_CTOR( mod_c ): 74 module_a("module_a"), 75 module_b("module_b") 76 { 77 78 module_a.in(input); 79 module_a.out(buf); 80 module_b.in(buf); 81 module_b.out(output); 82 83 } 84}; 85 86 87int 88sc_main( int, char*[] ) 89{ 90 mod_c c("c"); 91 cout << "binding of models to parent model is completed\n"; 92 return 0; 93} 94