test01.cpp revision 12855:588919e0e4aa 
1/*****************************************************************************
2
3  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
4  more contributor license agreements.  See the NOTICE file distributed
5  with this work for additional information regarding copyright ownership.
6  Accellera licenses this file to you under the Apache License, Version 2.0
7  (the "License"); you may not use this file except in compliance with the
8  License.  You may obtain a copy of the License at
9
10    http://www.apache.org/licenses/LICENSE-2.0
11
12  Unless required by applicable law or agreed to in writing, software
13  distributed under the License is distributed on an "AS IS" BASIS,
14  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
15  implied.  See the License for the specific language governing
16  permissions and limitations under the License.
17
18 *****************************************************************************/
19
20/*****************************************************************************
21
22  test01.cpp --
23
24  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25
26 *****************************************************************************/
27
28/*****************************************************************************
29
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
32
33      Name, Affiliation, Date:
34  Description of Modification:
35
36 *****************************************************************************/
37
38// test of named ports
39
40#include "systemc.h"
41
42SC_MODULE( mod_a )
43{
44    sc_in_clk    in_clk;
45    sc_inout_clk inout_clk;
46    sc_out_clk   out_clk;
47
48    sc_fifo_in<int>  fifo_in;
49    sc_fifo_out<int> fifo_out;
50
51    sc_port<sc_signal_in_if<float> > port;
52
53    sc_in<int>         in_int;
54    sc_in<bool>        in_bool;
55    sc_in<sc_logic>    in_logic;
56    sc_inout<int>      inout_int;
57    sc_inout<bool>     inout_bool;
58    sc_inout<sc_logic> inout_logic;
59    sc_out<int>        out_int;
60    sc_out<bool>       out_bool;
61    sc_out<sc_logic>   out_logic;
62
63    sc_in_resolved    in_resolved;
64    sc_inout_resolved inout_resolved;
65    sc_out_resolved   out_resolved;
66
67    sc_in_rv<1>    in_rv;
68    sc_inout_rv<1> inout_rv;
69    sc_out_rv<1>   out_rv;
70
71    SC_CTOR( mod_a )
72    : in_clk( "in_clk" ), inout_clk( "inout_clk" ), out_clk( "out_clk" ),
73      fifo_in( "fifo_in" ), fifo_out( "fifo_out" ),
74      port( "port" ),
75      in_int( "in_int" ), in_bool( "in_bool" ), in_logic( "in_logic" ),
76      inout_int( "inout_int" ), inout_bool( "inout_bool" ),
77      inout_logic( "inout_logic" ),
78      out_int( "out_int" ), out_bool( "out_bool" ), out_logic( "out_logic" ),
79      in_resolved( "in_resolved" ), inout_resolved( "inout_resolved" ),
80      out_resolved( "out_resolved" ),
81      in_rv( "in_rv" ), inout_rv( "inout_rv" ), out_rv( "out_rv" )
82    {}
83};
84
85#define WRITE(a) \
86    cout << a.name() << " (" << a.kind() << ")" << endl
87
88int
89sc_main( int, char*[] )
90{
91    mod_a a( "a" );
92
93    WRITE( a.in_clk );
94    WRITE( a.inout_clk );
95    WRITE( a.out_clk );
96
97    WRITE( a.fifo_in );
98    WRITE( a.fifo_out );
99
100    WRITE( a.port );
101
102    WRITE( a.in_int );
103    WRITE( a.in_bool );
104    WRITE( a.in_logic );
105    WRITE( a.inout_int );
106    WRITE( a.inout_bool );
107    WRITE( a.inout_logic );
108    WRITE( a.out_int );
109    WRITE( a.out_bool );
110    WRITE( a.out_logic );
111
112    WRITE( a.in_resolved );
113    WRITE( a.inout_resolved );
114    WRITE( a.out_resolved );
115
116    WRITE( a.in_rv );
117    WRITE( a.inout_rv );
118    WRITE( a.out_rv );
119
120    return 0;
121}
122