async_reset_port.cpp revision 12855:588919e0e4aa
1/***************************************************************************** 2 3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 4 more contributor license agreements. See the NOTICE file distributed 5 with this work for additional information regarding copyright ownership. 6 Accellera licenses this file to you under the Apache License, Version 2.0 7 (the "License"); you may not use this file except in compliance with the 8 License. You may obtain a copy of the License at 9 10 http://www.apache.org/licenses/LICENSE-2.0 11 12 Unless required by applicable law or agreed to in writing, software 13 distributed under the License is distributed on an "AS IS" BASIS, 14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 15 implied. See the License for the specific language governing 16 permissions and limitations under the License. 17 18 *****************************************************************************/ 19 20// async_reset_port.cpp -- 21// 22// Original Author: John Aynsley, Doulos Inc. 23// 24// MODIFICATION LOG - modifiers, enter your name, affiliation, date and 25// 26// $Log: async_reset_port.cpp,v $ 27// Revision 1.2 2011/05/08 19:18:46 acg 28// Andy Goodrich: remove extraneous + prefixes from git diff. 29// 30 31// async_reset_signal_is 32 33#define SC_INCLUDE_DYNAMIC_PROCESSES 34 35#include <systemc> 36using namespace sc_core; 37using std::cout; 38using std::endl; 39 40struct M: sc_module 41{ 42 sc_in<bool> clk; 43 44 sc_in<bool> sreset1; 45 sc_inout<bool> sreset2; 46 sc_out<bool> sreset3; 47 48 sc_in<bool> areset1; 49 sc_inout<bool> areset2; 50 sc_out<bool> areset3; 51 52 M(sc_module_name _name) 53 : count(0) 54 { 55 SC_CTHREAD(CT1, clk); 56 reset_signal_is(sreset1, false); 57 ct1 = sc_get_current_process_handle(); 58 59 SC_CTHREAD(CT2, clk); 60 reset_signal_is(sreset2, false); 61 ct2 = sc_get_current_process_handle(); 62 63 SC_CTHREAD(CT3, clk); 64 reset_signal_is(sreset3, false); 65 ct3 = sc_get_current_process_handle(); 66 67 SC_CTHREAD(CT4, clk); 68 async_reset_signal_is(areset1, false); 69 ct4 = sc_get_current_process_handle(); 70 71 SC_CTHREAD(CT5, clk); 72 async_reset_signal_is(areset2, false); 73 ct5 = sc_get_current_process_handle(); 74 75 SC_CTHREAD(CT6, clk); 76 async_reset_signal_is(areset3, false); 77 ct6 = sc_get_current_process_handle(); 78 79 f1 = f2 = f3 = f4 = f5 = f6 = f7 = f8 = f9 = 0; 80 f10 = f11 = f12 = f13 = f14 = f15 = f16 = f17 = f18 = f19 = 0; 81 f20 = f21 = f22 = f23 = f24 = f25 = f26 = f27 = f28 = f29 = 0; 82 f30 = f31 = f32 = f33 = f34 = f35 = f36 = f37 = f38 = f39 = 0; 83 } 84 85 int count; 86 sc_process_handle ct1, ct2, ct3, ct4, ct5, ct6; 87 88 int f1, f2, f3, f4, f5, f6, f7, f8, f9; 89 int f10, f11, f12, f13, f14, f15, f16, f17, f18, f19; 90 int f20, f21, f22, f23, f24, f25, f26, f27, f28, f29; 91 int f30, f31, f32, f33, f34, f35, f36, f37, f38, f39; 92 93 void CT1() 94 { 95 if (count == 2) { sc_assert(sc_time_stamp() == sc_time( 15, SC_NS)); f1 = 1; } 96 if (count == 17) { sc_assert(false); } 97 if (count == 18) { sc_assert(sc_time_stamp() == sc_time(135, SC_NS)); f16 = 1; } 98 if (count == 19) { sc_assert(sc_time_stamp() == sc_time(145, SC_NS)); f25 = 1; } 99 while (true) 100 { 101 wait(); 102 if (count == 16) { sc_assert(sc_time_stamp() == sc_time(125, SC_NS)); f10 = 1; } 103 if (count == 20) { sc_assert(sc_time_stamp() == sc_time(155, SC_NS)); f31 = 1; } 104 } 105 } 106 107 void CT2() 108 { 109 if (count == 4) { sc_assert(sc_time_stamp() == sc_time( 35, SC_NS)); f2 = 1; } 110 if (count == 17) { sc_assert(false); } 111 if (count == 18) { sc_assert(sc_time_stamp() == sc_time(135, SC_NS)); f17 = 1; } 112 if (count == 19) { sc_assert(sc_time_stamp() == sc_time(145, SC_NS)); f26 = 1; } 113 while (true) 114 { 115 wait(); 116 if (count == 16) { sc_assert(sc_time_stamp() == sc_time(125, SC_NS)); f11 = 1; } 117 if (count == 20) { sc_assert(sc_time_stamp() == sc_time(155, SC_NS)); f32 = 1; } 118 } 119 } 120 121 void CT3() 122 { 123 if (count == 6) { sc_assert(sc_time_stamp() == sc_time( 55, SC_NS)); f3 = 1; } 124 if (count == 17) { sc_assert(false); } 125 if (count == 18) { sc_assert(sc_time_stamp() == sc_time(135, SC_NS)); f18 = 1; } 126 if (count == 19) { sc_assert(sc_time_stamp() == sc_time(145, SC_NS)); f27 = 1; } 127 while (true) 128 { 129 wait(); 130 if (count == 16) { sc_assert(sc_time_stamp() == sc_time(125, SC_NS)); f12 = 1; } 131 if (count == 20) { sc_assert(sc_time_stamp() == sc_time(155, SC_NS)); f33 = 1; } 132 } 133 } 134 135 void CT4() 136 { 137 if (count == 8) { sc_assert(sc_time_stamp() == sc_time( 70, SC_NS)); f4 = 1; } 138 if (count == 9) { sc_assert(sc_time_stamp() == sc_time( 75, SC_NS)); f5 = 1; } 139 if (count == 17) { sc_assert(sc_time_stamp() == sc_time(130, SC_NS)); f19 = 1; } 140 if (count == 18) { sc_assert(sc_time_stamp() == sc_time(135, SC_NS)); f22 = 1; } 141 if (count == 19) { sc_assert(sc_time_stamp() == sc_time(145, SC_NS)); f28 = 1; } 142 while (true) 143 { 144 wait(); 145 if (count == 16) { sc_assert(sc_time_stamp() == sc_time(125, SC_NS)); f13 = 1; } 146 if (count == 20) { sc_assert(sc_time_stamp() == sc_time(155, SC_NS)); f34 = 1; } 147 } 148 } 149 150 void CT5() 151 { 152 if (count == 11) { sc_assert(sc_time_stamp() == sc_time( 90, SC_NS)); f6 = 1; } 153 if (count == 12) { sc_assert(sc_time_stamp() == sc_time( 95, SC_NS)); f7 = 1; } 154 if (count == 17) { sc_assert(sc_time_stamp() == sc_time(130, SC_NS)); f20 = 1; } 155 if (count == 18) { sc_assert(sc_time_stamp() == sc_time(135, SC_NS)); f23 = 1; } 156 if (count == 19) { sc_assert(sc_time_stamp() == sc_time(145, SC_NS)); f29 = 1; } 157 while (true) 158 { 159 wait(); 160 if (count == 16) { sc_assert(sc_time_stamp() == sc_time(125, SC_NS)); f14 = 1; } 161 if (count == 20) { sc_assert(sc_time_stamp() == sc_time(155, SC_NS)); f35 = 1; } 162 } 163 } 164 165 void CT6() 166 { 167 if (count == 14) { sc_assert(sc_time_stamp() == sc_time(110, SC_NS)); f8 = 1; } 168 if (count == 15) { sc_assert(sc_time_stamp() == sc_time(115, SC_NS)); f9 = 1; } 169 if (count == 17) { sc_assert(sc_time_stamp() == sc_time(130, SC_NS)); f21 = 1; } 170 if (count == 18) { sc_assert(sc_time_stamp() == sc_time(135, SC_NS)); f24 = 1; } 171 if (count == 19) { sc_assert(sc_time_stamp() == sc_time(145, SC_NS)); f30 = 1; } 172 while (true) 173 { 174 try { 175 wait(); 176 } 177 catch (const sc_unwind_exception& e) { 178 sc_assert( e.is_reset() ); 179 sc_assert( sc_is_unwinding() ); 180 if (count == 14) { sc_assert(sc_time_stamp() == sc_time(110, SC_NS)); f37 = 1; } 181 if (count == 17) { sc_assert(sc_time_stamp() == sc_time(130, SC_NS)); f38 = 1; } 182 throw e; 183 } 184 if (count == 16) { sc_assert(sc_time_stamp() == sc_time(125, SC_NS)); f15 = 1; } 185 if (count == 20) { sc_assert(sc_time_stamp() == sc_time(155, SC_NS)); f36 = 1; } 186 } 187 } 188 189 SC_HAS_PROCESS(M); 190}; 191 192struct Top: sc_module 193{ 194 Top(sc_module_name _name) 195 { 196 m = new M("m"); 197 m->clk(clk); 198 m->sreset1(sreset1); 199 m->sreset2(sreset2); 200 m->sreset3(sreset3); 201 m->areset1(areset1); 202 m->areset2(areset2); 203 m->areset3(areset3); 204 205 SC_THREAD(ctrl); 206 207 // Resets are all active-low 208 sreset1.write(1); 209 sreset2.write(1); 210 sreset3.write(1); 211 areset1.write(1); 212 areset2.write(1); 213 areset3.write(1); 214 } 215 216 M* m; 217 218 sc_signal<bool> clk; 219 220 sc_signal<bool> sreset1; 221 sc_signal<bool> sreset2; 222 sc_signal<bool> sreset3; 223 224 sc_signal<bool> areset1; 225 sc_signal<bool> areset2; 226 sc_signal<bool> areset3; 227 228 void ctrl() 229 { 230 m->count = 1; 231 clock(); 232 233 m->count = 2; 234 sreset1.write(0); 235 clock(); 236 237 m->count = 3; 238 sreset1.write(1); 239 clock(); 240 241 m->count = 4; 242 sreset2.write(0); 243 clock(); 244 245 m->count = 5; 246 sreset2.write(1); 247 clock(); 248 249 m->count = 6; 250 sreset3.write(0); 251 clock(); 252 253 m->count = 7; 254 sreset3.write(1); 255 clock(); 256 257 m->count = 8; 258 areset1.write(0); 259 wait(SC_ZERO_TIME); 260 261 m->count = 9; 262 clock(); 263 264 m->count = 10; 265 areset1.write(1); 266 clock(); 267 268 m->count = 11; 269 areset2.write(0); 270 wait(SC_ZERO_TIME); 271 272 m->count = 12; 273 clock(); 274 275 m->count = 13; 276 areset2.write(1); 277 clock(); 278 279 m->count = 14; 280 areset3.write(0); 281 wait(SC_ZERO_TIME); 282 283 m->count = 15; 284 clock(); 285 286 m->count = 16; 287 areset3.write(1); 288 clock(); 289 290 m->count = 17; 291 sreset1.write(0); 292 sreset2.write(0); 293 sreset3.write(0); 294 areset1.write(0); 295 areset2.write(0); 296 areset3.write(0); 297 wait(SC_ZERO_TIME); 298 299 m->count = 18; 300 clock(); 301 302 m->count = 19; 303 clock(); 304 305 m->count = 20; 306 sreset1.write(1); 307 sreset2.write(1); 308 sreset3.write(1); 309 areset1.write(1); 310 areset2.write(1); 311 areset3.write(1); 312 clock(); 313 } 314 315 void clock() 316 { 317 clk.write(0); 318 wait(5, SC_NS); 319 clk.write(1); 320 wait(5, SC_NS); 321 } 322 323 SC_HAS_PROCESS(Top); 324}; 325 326int sc_main(int argc, char* argv[]) 327{ 328 Top top("top"); 329 330 sc_start(); 331 332 sc_assert(top.m->f1); 333 sc_assert(top.m->f2); 334 sc_assert(top.m->f3); 335 sc_assert(top.m->f4); 336 sc_assert(top.m->f5); 337 sc_assert(top.m->f6); 338 sc_assert(top.m->f7); 339 sc_assert(top.m->f8); 340 sc_assert(top.m->f9); 341 sc_assert(top.m->f10); 342 sc_assert(top.m->f11); 343 sc_assert(top.m->f12); 344 sc_assert(top.m->f13); 345 sc_assert(top.m->f14); 346 sc_assert(top.m->f15); 347 sc_assert(top.m->f16); 348 sc_assert(top.m->f17); 349 sc_assert(top.m->f18); 350 sc_assert(top.m->f19); 351 sc_assert(top.m->f20); 352 sc_assert(top.m->f21); 353 sc_assert(top.m->f22); 354 sc_assert(top.m->f23); 355 sc_assert(top.m->f24); 356 sc_assert(top.m->f25); 357 sc_assert(top.m->f26); 358 sc_assert(top.m->f28); 359 sc_assert(top.m->f29); 360 sc_assert(top.m->f30); 361 sc_assert(top.m->f31); 362 sc_assert(top.m->f32); 363 sc_assert(top.m->f33); 364 sc_assert(top.m->f34); 365 sc_assert(top.m->f35); 366 sc_assert(top.m->f36); 367 sc_assert(top.m->f37); 368 sc_assert(top.m->f38); 369 370 cout << endl << "Success" << endl; 371 return 0; 372} 373