vptr.hh revision 2680
1712SN/A/* 21762SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 3712SN/A * All rights reserved. 4712SN/A * 5712SN/A * Redistribution and use in source and binary forms, with or without 6712SN/A * modification, are permitted provided that the following conditions are 7712SN/A * met: redistributions of source code must retain the above copyright 8712SN/A * notice, this list of conditions and the following disclaimer; 9712SN/A * redistributions in binary form must reproduce the above copyright 10712SN/A * notice, this list of conditions and the following disclaimer in the 11712SN/A * documentation and/or other materials provided with the distribution; 12712SN/A * neither the name of the copyright holders nor the names of its 13712SN/A * contributors may be used to endorse or promote products derived from 14712SN/A * this software without specific prior written permission. 15712SN/A * 16712SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17712SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18712SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19712SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20712SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21712SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22712SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23712SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24712SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25712SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26712SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Nathan Binkert 29712SN/A */ 30712SN/A 311354SN/A#ifndef __ARCH_ALPHA_VPTR_HH__ 321354SN/A#define __ARCH_ALPHA_VPTR_HH__ 33712SN/A 342170SN/A#include "arch/vtophys.hh" 352080SN/A#include "arch/isa_traits.hh" 36712SN/A 372680Sktlim@umich.educlass ThreadContext; 38712SN/A 39712SN/Atemplate <class T> 40712SN/Aclass VPtr 41712SN/A{ 42712SN/A public: 43712SN/A typedef T Type; 44712SN/A 45712SN/A private: 462680Sktlim@umich.edu ThreadContext *tc; 47712SN/A Addr ptr; 48712SN/A 49712SN/A public: 502680Sktlim@umich.edu ThreadContext *GetTC() const { return tc; } 51712SN/A Addr GetPointer() const { return ptr; } 52712SN/A 53712SN/A public: 542680Sktlim@umich.edu explicit VPtr(ThreadContext *_tc, Addr p = 0) : tc(_tc), ptr(p) { } 55712SN/A template <class U> 562680Sktlim@umich.edu VPtr(const VPtr<U> &vp) : tc(vp.GetTC()), ptr(vp.GetPointer()) {} 57712SN/A ~VPtr() {} 58712SN/A 59712SN/A bool operator!() const 60712SN/A { 61712SN/A return ptr == 0; 62712SN/A } 63712SN/A 64712SN/A VPtr<T> operator+(int offset) 65712SN/A { 66712SN/A VPtr<T> ptr(*this); 67712SN/A ptr += offset; 68712SN/A 69712SN/A return ptr; 70712SN/A } 71712SN/A 72712SN/A const VPtr<T> &operator+=(int offset) 73712SN/A { 74712SN/A ptr += offset; 752080SN/A assert((ptr & (TheISA::PageBytes - 1)) + sizeof(T) 762080SN/A < TheISA::PageBytes); 77712SN/A 78712SN/A return *this; 79712SN/A } 80712SN/A 81712SN/A const VPtr<T> &operator=(Addr p) 82712SN/A { 832080SN/A assert((p & (TheISA::PageBytes - 1)) + sizeof(T) 842080SN/A < TheISA::PageBytes); 85712SN/A ptr = p; 86712SN/A 87712SN/A return *this; 88712SN/A } 89712SN/A 90712SN/A template <class U> 91712SN/A const VPtr<T> &operator=(const VPtr<U> &vp) 92712SN/A { 932680Sktlim@umich.edu tc = vp.GetTC(); 94712SN/A ptr = vp.GetPointer(); 95712SN/A 96712SN/A return *this; 97712SN/A } 98712SN/A 99712SN/A operator T *() 100712SN/A { 1012521SN/A panic("Needs to be rewritten\n"); 1022680Sktlim@umich.edu/* void *addr = vtomem(tc, ptr, sizeof(T)); 103712SN/A return (T *)addr; 1042521SN/A */ 105712SN/A } 106712SN/A 107712SN/A T *operator->() 108712SN/A { 1092521SN/A panic("Needs to be rewritten\n"); 1102680Sktlim@umich.edu/* void *addr = vtomem(tc, ptr, sizeof(T)); 111712SN/A return (T *)addr; 1122521SN/A */ 113712SN/A } 114712SN/A 115712SN/A T &operator*() 116712SN/A { 1172521SN/A panic("Needs to be rewritten\n"); 1182680Sktlim@umich.edu/* void *addr = vtomem(tc, ptr, sizeof(T)); 119712SN/A return *(T *)addr; 1202521SN/A */ 121712SN/A } 122712SN/A}; 123712SN/A 1241354SN/A#endif // __ARCH_ALPHA_VPTR_HH__ 125