system.hh revision 12515:e3d1a64d0260
1/* 2 * Copyright (c) 2012, 2014 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * Copyright (c) 2011 Regents of the University of California 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Steve Reinhardt 42 * Lisa Hsu 43 * Nathan Binkert 44 * Rick Strong 45 */ 46 47#ifndef __SYSTEM_HH__ 48#define __SYSTEM_HH__ 49 50#include <string> 51#include <unordered_map> 52#include <utility> 53#include <vector> 54 55#include "arch/isa_traits.hh" 56#include "base/loader/symtab.hh" 57#include "base/statistics.hh" 58#include "config/the_isa.hh" 59#include "enums/MemoryMode.hh" 60#include "mem/mem_object.hh" 61#include "mem/physical.hh" 62#include "mem/port.hh" 63#include "mem/port_proxy.hh" 64#include "params/System.hh" 65#include "sim/futex_map.hh" 66#include "sim/se_signal.hh" 67 68/** 69 * To avoid linking errors with LTO, only include the header if we 70 * actually have the definition. 71 */ 72#if THE_ISA != NULL_ISA 73#include "cpu/pc_event.hh" 74 75#endif 76 77class BaseRemoteGDB; 78class KvmVM; 79class ObjectFile; 80class ThreadContext; 81 82class System : public MemObject 83{ 84 private: 85 86 /** 87 * Private class for the system port which is only used as a 88 * master for debug access and for non-structural entities that do 89 * not have a port of their own. 90 */ 91 class SystemPort : public MasterPort 92 { 93 public: 94 95 /** 96 * Create a system port with a name and an owner. 97 */ 98 SystemPort(const std::string &_name, MemObject *_owner) 99 : MasterPort(_name, _owner) 100 { } 101 bool recvTimingResp(PacketPtr pkt) override 102 { panic("SystemPort does not receive timing!\n"); return false; } 103 void recvReqRetry() override 104 { panic("SystemPort does not expect retry!\n"); } 105 }; 106 107 SystemPort _systemPort; 108 109 public: 110 111 /** 112 * After all objects have been created and all ports are 113 * connected, check that the system port is connected. 114 */ 115 void init() override; 116 117 /** 118 * Get a reference to the system port that can be used by 119 * non-structural simulation objects like processes or threads, or 120 * external entities like loaders and debuggers, etc, to access 121 * the memory system. 122 * 123 * @return a reference to the system port we own 124 */ 125 MasterPort& getSystemPort() { return _systemPort; } 126 127 /** 128 * Additional function to return the Port of a memory object. 129 */ 130 BaseMasterPort& getMasterPort(const std::string &if_name, 131 PortID idx = InvalidPortID) override; 132 133 /** @{ */ 134 /** 135 * Is the system in atomic mode? 136 * 137 * There are currently two different atomic memory modes: 138 * 'atomic', which supports caches; and 'atomic_noncaching', which 139 * bypasses caches. The latter is used by hardware virtualized 140 * CPUs. SimObjects are expected to use Port::sendAtomic() and 141 * Port::recvAtomic() when accessing memory in this mode. 142 */ 143 bool isAtomicMode() const { 144 return memoryMode == Enums::atomic || 145 memoryMode == Enums::atomic_noncaching; 146 } 147 148 /** 149 * Is the system in timing mode? 150 * 151 * SimObjects are expected to use Port::sendTiming() and 152 * Port::recvTiming() when accessing memory in this mode. 153 */ 154 bool isTimingMode() const { 155 return memoryMode == Enums::timing; 156 } 157 158 /** 159 * Should caches be bypassed? 160 * 161 * Some CPUs need to bypass caches to allow direct memory 162 * accesses, which is required for hardware virtualization. 163 */ 164 bool bypassCaches() const { 165 return memoryMode == Enums::atomic_noncaching; 166 } 167 /** @} */ 168 169 /** @{ */ 170 /** 171 * Get the memory mode of the system. 172 * 173 * \warn This should only be used by the Python world. The C++ 174 * world should use one of the query functions above 175 * (isAtomicMode(), isTimingMode(), bypassCaches()). 176 */ 177 Enums::MemoryMode getMemoryMode() const { return memoryMode; } 178 179 /** 180 * Change the memory mode of the system. 181 * 182 * \warn This should only be called by the Python! 183 * 184 * @param mode Mode to change to (atomic/timing/...) 185 */ 186 void setMemoryMode(Enums::MemoryMode mode); 187 /** @} */ 188 189 /** 190 * Get the cache line size of the system. 191 */ 192 unsigned int cacheLineSize() const { return _cacheLineSize; } 193 194#if THE_ISA != NULL_ISA 195 PCEventQueue pcEventQueue; 196#endif 197 198 std::vector<ThreadContext *> threadContexts; 199 const bool multiThread; 200 201 ThreadContext *getThreadContext(ContextID tid) 202 { 203 return threadContexts[tid]; 204 } 205 206 unsigned numContexts() const { return threadContexts.size(); } 207 208 /** Return number of running (non-halted) thread contexts in 209 * system. These threads could be Active or Suspended. */ 210 int numRunningContexts(); 211 212 Addr pagePtr; 213 214 uint64_t init_param; 215 216 /** Port to physical memory used for writing object files into ram at 217 * boot.*/ 218 PortProxy physProxy; 219 220 /** kernel symbol table */ 221 SymbolTable *kernelSymtab; 222 223 /** Object pointer for the kernel code */ 224 ObjectFile *kernel; 225 226 /** Additional object files */ 227 std::vector<ObjectFile *> kernelExtras; 228 229 /** Beginning of kernel code */ 230 Addr kernelStart; 231 232 /** End of kernel code */ 233 Addr kernelEnd; 234 235 /** Entry point in the kernel to start at */ 236 Addr kernelEntry; 237 238 /** Mask that should be anded for binary/symbol loading. 239 * This allows one two different OS requirements for the same ISA to be 240 * handled. Some OSes are compiled for a virtual address and need to be 241 * loaded into physical memory that starts at address 0, while other 242 * bare metal tools generate images that start at address 0. 243 */ 244 Addr loadAddrMask; 245 246 /** Offset that should be used for binary/symbol loading. 247 * This further allows more flexibility than the loadAddrMask allows alone 248 * in loading kernels and similar. The loadAddrOffset is applied after the 249 * loadAddrMask. 250 */ 251 Addr loadAddrOffset; 252 253 public: 254 /** 255 * Get a pointer to the Kernel Virtual Machine (KVM) SimObject, 256 * if present. 257 */ 258 KvmVM* getKvmVM() { 259 return kvmVM; 260 } 261 262 /** Verify gem5 configuration will support KVM emulation */ 263 bool validKvmEnvironment() const; 264 265 /** Get a pointer to access the physical memory of the system */ 266 PhysicalMemory& getPhysMem() { return physmem; } 267 268 /** Amount of physical memory that is still free */ 269 Addr freeMemSize() const; 270 271 /** Amount of physical memory that exists */ 272 Addr memSize() const; 273 274 /** 275 * Check if a physical address is within a range of a memory that 276 * is part of the global address map. 277 * 278 * @param addr A physical address 279 * @return Whether the address corresponds to a memory 280 */ 281 bool isMemAddr(Addr addr) const; 282 283 /** 284 * Get the architecture. 285 */ 286 Arch getArch() const { return Arch::TheISA; } 287 288 /** 289 * Get the page bytes for the ISA. 290 */ 291 Addr getPageBytes() const { return TheISA::PageBytes; } 292 293 /** 294 * Get the number of bits worth of in-page address for the ISA. 295 */ 296 Addr getPageShift() const { return TheISA::PageShift; } 297 298 /** 299 * The thermal model used for this system (if any). 300 */ 301 ThermalModel * getThermalModel() const { return thermalModel; } 302 303 protected: 304 305 KvmVM *const kvmVM; 306 307 PhysicalMemory physmem; 308 309 Enums::MemoryMode memoryMode; 310 311 const unsigned int _cacheLineSize; 312 313 uint64_t workItemsBegin; 314 uint64_t workItemsEnd; 315 uint32_t numWorkIds; 316 std::vector<bool> activeCpus; 317 318 /** This array is a per-system list of all devices capable of issuing a 319 * memory system request and an associated string for each master id. 320 * It's used to uniquely id any master in the system by name for things 321 * like cache statistics. 322 */ 323 std::vector<std::string> masterIds; 324 325 ThermalModel * thermalModel; 326 327 public: 328 329 /** Request an id used to create a request object in the system. All objects 330 * that intend to issues requests into the memory system must request an id 331 * in the init() phase of startup. All master ids must be fixed by the 332 * regStats() phase that immediately precedes it. This allows objects in 333 * the memory system to understand how many masters may exist and 334 * appropriately name the bins of their per-master stats before the stats 335 * are finalized 336 */ 337 MasterID getMasterId(std::string req_name); 338 339 /** Get the name of an object for a given request id. 340 */ 341 std::string getMasterName(MasterID master_id); 342 343 /** Get the number of masters registered in the system */ 344 MasterID maxMasters() 345 { 346 return masterIds.size(); 347 } 348 349 void regStats() override; 350 /** 351 * Called by pseudo_inst to track the number of work items started by this 352 * system. 353 */ 354 uint64_t 355 incWorkItemsBegin() 356 { 357 return ++workItemsBegin; 358 } 359 360 /** 361 * Called by pseudo_inst to track the number of work items completed by 362 * this system. 363 */ 364 uint64_t 365 incWorkItemsEnd() 366 { 367 return ++workItemsEnd; 368 } 369 370 /** 371 * Called by pseudo_inst to mark the cpus actively executing work items. 372 * Returns the total number of cpus that have executed work item begin or 373 * ends. 374 */ 375 int 376 markWorkItem(int index) 377 { 378 int count = 0; 379 assert(index < activeCpus.size()); 380 activeCpus[index] = true; 381 for (std::vector<bool>::iterator i = activeCpus.begin(); 382 i < activeCpus.end(); i++) { 383 if (*i) count++; 384 } 385 return count; 386 } 387 388 inline void workItemBegin(uint32_t tid, uint32_t workid) 389 { 390 std::pair<uint32_t,uint32_t> p(tid, workid); 391 lastWorkItemStarted[p] = curTick(); 392 } 393 394 void workItemEnd(uint32_t tid, uint32_t workid); 395 396 /** 397 * Fix up an address used to match PCs for hooking simulator 398 * events on to target function executions. See comment in 399 * system.cc for details. 400 */ 401 virtual Addr fixFuncEventAddr(Addr addr) 402 { 403 panic("Base fixFuncEventAddr not implemented.\n"); 404 } 405 406 /** @{ */ 407 /** 408 * Add a function-based event to the given function, to be looked 409 * up in the specified symbol table. 410 * 411 * The ...OrPanic flavor of the method causes the simulator to 412 * panic if the symbol can't be found. 413 * 414 * @param symtab Symbol table to use for look up. 415 * @param lbl Function to hook the event to. 416 * @param desc Description to be passed to the event. 417 * @param args Arguments to be forwarded to the event constructor. 418 */ 419 template <class T, typename... Args> 420 T *addFuncEvent(const SymbolTable *symtab, const char *lbl, 421 const std::string &desc, Args... args) 422 { 423 Addr addr M5_VAR_USED = 0; // initialize only to avoid compiler warning 424 425#if THE_ISA != NULL_ISA 426 if (symtab->findAddress(lbl, addr)) { 427 T *ev = new T(&pcEventQueue, desc, fixFuncEventAddr(addr), 428 std::forward<Args>(args)...); 429 return ev; 430 } 431#endif 432 433 return NULL; 434 } 435 436 template <class T> 437 T *addFuncEvent(const SymbolTable *symtab, const char *lbl) 438 { 439 return addFuncEvent<T>(symtab, lbl, lbl); 440 } 441 442 template <class T, typename... Args> 443 T *addFuncEventOrPanic(const SymbolTable *symtab, const char *lbl, 444 Args... args) 445 { 446 T *e(addFuncEvent<T>(symtab, lbl, std::forward<Args>(args)...)); 447 if (!e) 448 panic("Failed to find symbol '%s'", lbl); 449 return e; 450 } 451 /** @} */ 452 453 /** @{ */ 454 /** 455 * Add a function-based event to a kernel symbol. 456 * 457 * These functions work like their addFuncEvent() and 458 * addFuncEventOrPanic() counterparts. The only difference is that 459 * they automatically use the kernel symbol table. All arguments 460 * are forwarded to the underlying method. 461 * 462 * @see addFuncEvent() 463 * @see addFuncEventOrPanic() 464 * 465 * @param lbl Function to hook the event to. 466 * @param args Arguments to be passed to addFuncEvent 467 */ 468 template <class T, typename... Args> 469 T *addKernelFuncEvent(const char *lbl, Args... args) 470 { 471 return addFuncEvent<T>(kernelSymtab, lbl, 472 std::forward<Args>(args)...); 473 } 474 475 template <class T, typename... Args> 476 T *addKernelFuncEventOrPanic(const char *lbl, Args... args) 477 { 478 T *e(addFuncEvent<T>(kernelSymtab, lbl, 479 std::forward<Args>(args)...)); 480 if (!e) 481 panic("Failed to find kernel symbol '%s'", lbl); 482 return e; 483 } 484 /** @} */ 485 486 public: 487 std::vector<BaseRemoteGDB *> remoteGDB; 488 bool breakpoint(); 489 490 public: 491 typedef SystemParams Params; 492 493 protected: 494 Params *_params; 495 496 public: 497 System(Params *p); 498 ~System(); 499 500 void initState() override; 501 502 const Params *params() const { return (const Params *)_params; } 503 504 public: 505 506 /** 507 * Returns the address the kernel starts at. 508 * @return address the kernel starts at 509 */ 510 Addr getKernelStart() const { return kernelStart; } 511 512 /** 513 * Returns the address the kernel ends at. 514 * @return address the kernel ends at 515 */ 516 Addr getKernelEnd() const { return kernelEnd; } 517 518 /** 519 * Returns the address the entry point to the kernel code. 520 * @return entry point of the kernel code 521 */ 522 Addr getKernelEntry() const { return kernelEntry; } 523 524 /// Allocate npages contiguous unused physical pages 525 /// @return Starting address of first page 526 Addr allocPhysPages(int npages); 527 528 ContextID registerThreadContext(ThreadContext *tc, 529 ContextID assigned = InvalidContextID); 530 void replaceThreadContext(ThreadContext *tc, ContextID context_id); 531 532 void serialize(CheckpointOut &cp) const override; 533 void unserialize(CheckpointIn &cp) override; 534 535 void drainResume() override; 536 537 public: 538 Counter totalNumInsts; 539 EventQueue instEventQueue; 540 std::map<std::pair<uint32_t,uint32_t>, Tick> lastWorkItemStarted; 541 std::map<uint32_t, Stats::Histogram*> workItemStats; 542 543 //////////////////////////////////////////// 544 // 545 // STATIC GLOBAL SYSTEM LIST 546 // 547 //////////////////////////////////////////// 548 549 static std::vector<System *> systemList; 550 static int numSystemsRunning; 551 552 static void printSystems(); 553 554 FutexMap futexMap; 555 556 static const int maxPID = 32768; 557 558 /** Process set to track which PIDs have already been allocated */ 559 std::set<int> PIDs; 560 561 // By convention, all signals are owned by the receiving process. The 562 // receiver will delete the signal upon reception. 563 std::list<BasicSignal> signalList; 564 565 protected: 566 567 /** 568 * If needed, serialize additional symbol table entries for a 569 * specific subclass of this system. Currently this is used by 570 * Alpha and MIPS. 571 * 572 * @param os stream to serialize to 573 */ 574 virtual void serializeSymtab(CheckpointOut &os) const {} 575 576 /** 577 * If needed, unserialize additional symbol table entries for a 578 * specific subclass of this system. 579 * 580 * @param cp checkpoint to unserialize from 581 * @param section relevant section in the checkpoint 582 */ 583 virtual void unserializeSymtab(CheckpointIn &cp) {} 584 585}; 586 587void printSystems(); 588 589#endif // __SYSTEM_HH__ 590