system.hh revision 9850
12SN/A/* 28703Sandreas.hansson@arm.com * Copyright (c) 2012 ARM Limited 38703Sandreas.hansson@arm.com * All rights reserved 48703Sandreas.hansson@arm.com * 58703Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68703Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78703Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88703Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98703Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108703Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118703Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128703Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138703Sandreas.hansson@arm.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422665Ssaidi@eecs.umich.edu * Lisa Hsu 432665Ssaidi@eecs.umich.edu * Nathan Binkert 447897Shestness@cs.utexas.edu * Rick Strong 452SN/A */ 462SN/A 472SN/A#ifndef __SYSTEM_HH__ 482SN/A#define __SYSTEM_HH__ 492SN/A 502SN/A#include <string> 519645SAndreas.Sandberg@ARM.com#include <utility> 5275SN/A#include <vector> 532SN/A 542439SN/A#include "base/loader/symtab.hh" 552439SN/A#include "base/misc.hh" 56603SN/A#include "base/statistics.hh" 57603SN/A#include "cpu/pc_event.hh" 584762Snate@binkert.org#include "enums/MemoryMode.hh" 598769Sgblack@eecs.umich.edu#include "kern/system_events.hh" 608703Sandreas.hansson@arm.com#include "mem/mem_object.hh" 612520SN/A#include "mem/port.hh" 629847Sandreas.hansson@arm.com#include "mem/port_proxy.hh" 638931Sandreas.hansson@arm.com#include "mem/physical.hh" 644762Snate@binkert.org#include "params/System.hh" 656658Snate@binkert.org 661634SN/Aclass BaseCPU; 678769Sgblack@eecs.umich.educlass BaseRemoteGDB; 688769Sgblack@eecs.umich.educlass GDBListener; 691634SN/Aclass ObjectFile; 70803SN/Aclass Platform; 718769Sgblack@eecs.umich.educlass ThreadContext; 722SN/A 738703Sandreas.hansson@arm.comclass System : public MemObject 742SN/A{ 758703Sandreas.hansson@arm.com private: 768703Sandreas.hansson@arm.com 778703Sandreas.hansson@arm.com /** 788703Sandreas.hansson@arm.com * Private class for the system port which is only used as a 798703Sandreas.hansson@arm.com * master for debug access and for non-structural entities that do 808703Sandreas.hansson@arm.com * not have a port of their own. 818703Sandreas.hansson@arm.com */ 828922Swilliam.wang@arm.com class SystemPort : public MasterPort 838703Sandreas.hansson@arm.com { 848703Sandreas.hansson@arm.com public: 858703Sandreas.hansson@arm.com 868703Sandreas.hansson@arm.com /** 878703Sandreas.hansson@arm.com * Create a system port with a name and an owner. 888703Sandreas.hansson@arm.com */ 898703Sandreas.hansson@arm.com SystemPort(const std::string &_name, MemObject *_owner) 908922Swilliam.wang@arm.com : MasterPort(_name, _owner) 918703Sandreas.hansson@arm.com { } 928975Sandreas.hansson@arm.com bool recvTimingResp(PacketPtr pkt) 938703Sandreas.hansson@arm.com { panic("SystemPort does not receive timing!\n"); return false; } 948922Swilliam.wang@arm.com void recvRetry() 958922Swilliam.wang@arm.com { panic("SystemPort does not expect retry!\n"); } 968703Sandreas.hansson@arm.com }; 978703Sandreas.hansson@arm.com 988703Sandreas.hansson@arm.com SystemPort _systemPort; 998703Sandreas.hansson@arm.com 100603SN/A public: 1012901Ssaidi@eecs.umich.edu 1028703Sandreas.hansson@arm.com /** 1038706Sandreas.hansson@arm.com * After all objects have been created and all ports are 1048706Sandreas.hansson@arm.com * connected, check that the system port is connected. 1058706Sandreas.hansson@arm.com */ 1068706Sandreas.hansson@arm.com virtual void init(); 1078706Sandreas.hansson@arm.com 1088706Sandreas.hansson@arm.com /** 1098852Sandreas.hansson@arm.com * Get a reference to the system port that can be used by 1108703Sandreas.hansson@arm.com * non-structural simulation objects like processes or threads, or 1118703Sandreas.hansson@arm.com * external entities like loaders and debuggers, etc, to access 1128703Sandreas.hansson@arm.com * the memory system. 1138703Sandreas.hansson@arm.com * 1148852Sandreas.hansson@arm.com * @return a reference to the system port we own 1158703Sandreas.hansson@arm.com */ 1168922Swilliam.wang@arm.com MasterPort& getSystemPort() { return _systemPort; } 1178703Sandreas.hansson@arm.com 1188703Sandreas.hansson@arm.com /** 1198703Sandreas.hansson@arm.com * Additional function to return the Port of a memory object. 1208703Sandreas.hansson@arm.com */ 1219294Sandreas.hansson@arm.com BaseMasterPort& getMasterPort(const std::string &if_name, 1229294Sandreas.hansson@arm.com PortID idx = InvalidPortID); 1238703Sandreas.hansson@arm.com 1249524SAndreas.Sandberg@ARM.com static const char *MemoryModeStrings[4]; 1252902Ssaidi@eecs.umich.edu 1269524SAndreas.Sandberg@ARM.com /** @{ */ 1279524SAndreas.Sandberg@ARM.com /** 1289524SAndreas.Sandberg@ARM.com * Is the system in atomic mode? 1299524SAndreas.Sandberg@ARM.com * 1309524SAndreas.Sandberg@ARM.com * There are currently two different atomic memory modes: 1319524SAndreas.Sandberg@ARM.com * 'atomic', which supports caches; and 'atomic_noncaching', which 1329524SAndreas.Sandberg@ARM.com * bypasses caches. The latter is used by hardware virtualized 1339524SAndreas.Sandberg@ARM.com * CPUs. SimObjects are expected to use Port::sendAtomic() and 1349524SAndreas.Sandberg@ARM.com * Port::recvAtomic() when accessing memory in this mode. 1359524SAndreas.Sandberg@ARM.com */ 1369524SAndreas.Sandberg@ARM.com bool isAtomicMode() const { 1379524SAndreas.Sandberg@ARM.com return memoryMode == Enums::atomic || 1389524SAndreas.Sandberg@ARM.com memoryMode == Enums::atomic_noncaching; 1394762Snate@binkert.org } 1402901Ssaidi@eecs.umich.edu 1419524SAndreas.Sandberg@ARM.com /** 1429524SAndreas.Sandberg@ARM.com * Is the system in timing mode? 1439524SAndreas.Sandberg@ARM.com * 1449524SAndreas.Sandberg@ARM.com * SimObjects are expected to use Port::sendTiming() and 1459524SAndreas.Sandberg@ARM.com * Port::recvTiming() when accessing memory in this mode. 1469524SAndreas.Sandberg@ARM.com */ 1479524SAndreas.Sandberg@ARM.com bool isTimingMode() const { 1489524SAndreas.Sandberg@ARM.com return memoryMode == Enums::timing; 1499524SAndreas.Sandberg@ARM.com } 1509524SAndreas.Sandberg@ARM.com 1519524SAndreas.Sandberg@ARM.com /** 1529524SAndreas.Sandberg@ARM.com * Should caches be bypassed? 1539524SAndreas.Sandberg@ARM.com * 1549524SAndreas.Sandberg@ARM.com * Some CPUs need to bypass caches to allow direct memory 1559524SAndreas.Sandberg@ARM.com * accesses, which is required for hardware virtualization. 1569524SAndreas.Sandberg@ARM.com */ 1579524SAndreas.Sandberg@ARM.com bool bypassCaches() const { 1589524SAndreas.Sandberg@ARM.com return memoryMode == Enums::atomic_noncaching; 1599524SAndreas.Sandberg@ARM.com } 1609524SAndreas.Sandberg@ARM.com /** @} */ 1619524SAndreas.Sandberg@ARM.com 1629524SAndreas.Sandberg@ARM.com /** @{ */ 1639524SAndreas.Sandberg@ARM.com /** 1649524SAndreas.Sandberg@ARM.com * Get the memory mode of the system. 1659524SAndreas.Sandberg@ARM.com * 1669524SAndreas.Sandberg@ARM.com * \warn This should only be used by the Python world. The C++ 1679524SAndreas.Sandberg@ARM.com * world should use one of the query functions above 1689524SAndreas.Sandberg@ARM.com * (isAtomicMode(), isTimingMode(), bypassCaches()). 1699524SAndreas.Sandberg@ARM.com */ 1709524SAndreas.Sandberg@ARM.com Enums::MemoryMode getMemoryMode() const { return memoryMode; } 1719524SAndreas.Sandberg@ARM.com 1729524SAndreas.Sandberg@ARM.com /** 1739524SAndreas.Sandberg@ARM.com * Change the memory mode of the system. 1749524SAndreas.Sandberg@ARM.com * 1759524SAndreas.Sandberg@ARM.com * \warn This should only be called by the Python! 1769524SAndreas.Sandberg@ARM.com * 1779524SAndreas.Sandberg@ARM.com * @param mode Mode to change to (atomic/timing/...) 1782901Ssaidi@eecs.umich.edu */ 1794762Snate@binkert.org void setMemoryMode(Enums::MemoryMode mode); 1809524SAndreas.Sandberg@ARM.com /** @} */ 1812901Ssaidi@eecs.umich.edu 1829814Sandreas.hansson@arm.com /** 1839814Sandreas.hansson@arm.com * Get the cache line size of the system. 1849814Sandreas.hansson@arm.com */ 1859814Sandreas.hansson@arm.com unsigned int cacheLineSize() const { return _cacheLineSize; } 1869814Sandreas.hansson@arm.com 1879850Sandreas.hansson@arm.com#if THE_ISA != NULL_ISA 1882SN/A PCEventQueue pcEventQueue; 1899850Sandreas.hansson@arm.com#endif 1902SN/A 1912680Sktlim@umich.edu std::vector<ThreadContext *> threadContexts; 1925714Shsul@eecs.umich.edu int _numContexts; 1931806SN/A 1946221Snate@binkert.org ThreadContext *getThreadContext(ThreadID tid) 1955713Shsul@eecs.umich.edu { 1965713Shsul@eecs.umich.edu return threadContexts[tid]; 1975713Shsul@eecs.umich.edu } 1985713Shsul@eecs.umich.edu 1995714Shsul@eecs.umich.edu int numContexts() 2001806SN/A { 2016227Snate@binkert.org assert(_numContexts == (int)threadContexts.size()); 2025714Shsul@eecs.umich.edu return _numContexts; 2031806SN/A } 204180SN/A 2056029Ssteve.reinhardt@amd.com /** Return number of running (non-halted) thread contexts in 2066029Ssteve.reinhardt@amd.com * system. These threads could be Active or Suspended. */ 2076029Ssteve.reinhardt@amd.com int numRunningContexts(); 2086029Ssteve.reinhardt@amd.com 2098765Sgblack@eecs.umich.edu Addr pagePtr; 2108765Sgblack@eecs.umich.edu 2112378SN/A uint64_t init_param; 2122378SN/A 2132520SN/A /** Port to physical memory used for writing object files into ram at 2142520SN/A * boot.*/ 2158852Sandreas.hansson@arm.com PortProxy physProxy; 2162520SN/A 2171885SN/A /** kernel symbol table */ 2181070SN/A SymbolTable *kernelSymtab; 219954SN/A 2201070SN/A /** Object pointer for the kernel code */ 2211070SN/A ObjectFile *kernel; 2221070SN/A 2231070SN/A /** Begining of kernel code */ 2241070SN/A Addr kernelStart; 2251070SN/A 2261070SN/A /** End of kernel code */ 2271070SN/A Addr kernelEnd; 2281070SN/A 2291070SN/A /** Entry point in the kernel to start at */ 2301070SN/A Addr kernelEntry; 2311070SN/A 2327580SAli.Saidi@arm.com /** Mask that should be anded for binary/symbol loading. 2337580SAli.Saidi@arm.com * This allows one two different OS requirements for the same ISA to be 2347580SAli.Saidi@arm.com * handled. Some OSes are compiled for a virtual address and need to be 2357580SAli.Saidi@arm.com * loaded into physical memory that starts at address 0, while other 2367580SAli.Saidi@arm.com * bare metal tools generate images that start at address 0. 2377580SAli.Saidi@arm.com */ 2387580SAli.Saidi@arm.com Addr loadAddrMask; 2397580SAli.Saidi@arm.com 2404997Sgblack@eecs.umich.edu protected: 2417770SAli.Saidi@ARM.com uint64_t nextPID; 2424997Sgblack@eecs.umich.edu 2434997Sgblack@eecs.umich.edu public: 2444997Sgblack@eecs.umich.edu uint64_t allocatePID() 2454997Sgblack@eecs.umich.edu { 2467770SAli.Saidi@ARM.com return nextPID++; 2474997Sgblack@eecs.umich.edu } 2484997Sgblack@eecs.umich.edu 2498931Sandreas.hansson@arm.com /** Get a pointer to access the physical memory of the system */ 2508931Sandreas.hansson@arm.com PhysicalMemory& getPhysMem() { return physmem; } 2518931Sandreas.hansson@arm.com 2525795Ssaidi@eecs.umich.edu /** Amount of physical memory that is still free */ 2538931Sandreas.hansson@arm.com Addr freeMemSize() const; 2545795Ssaidi@eecs.umich.edu 2555795Ssaidi@eecs.umich.edu /** Amount of physical memory that exists */ 2568931Sandreas.hansson@arm.com Addr memSize() const; 2578931Sandreas.hansson@arm.com 2588931Sandreas.hansson@arm.com /** 2598931Sandreas.hansson@arm.com * Check if a physical address is within a range of a memory that 2608931Sandreas.hansson@arm.com * is part of the global address map. 2618931Sandreas.hansson@arm.com * 2628931Sandreas.hansson@arm.com * @param addr A physical address 2638931Sandreas.hansson@arm.com * @return Whether the address corresponds to a memory 2648931Sandreas.hansson@arm.com */ 2658931Sandreas.hansson@arm.com bool isMemAddr(Addr addr) const; 2665795Ssaidi@eecs.umich.edu 2671885SN/A protected: 2688931Sandreas.hansson@arm.com 2698931Sandreas.hansson@arm.com PhysicalMemory physmem; 2708931Sandreas.hansson@arm.com 2714762Snate@binkert.org Enums::MemoryMode memoryMode; 2729814Sandreas.hansson@arm.com 2739814Sandreas.hansson@arm.com const unsigned int _cacheLineSize; 2749814Sandreas.hansson@arm.com 2757914SBrad.Beckmann@amd.com uint64_t workItemsBegin; 2767914SBrad.Beckmann@amd.com uint64_t workItemsEnd; 2778666SPrakash.Ramrakhyani@arm.com uint32_t numWorkIds; 2787914SBrad.Beckmann@amd.com std::vector<bool> activeCpus; 2797914SBrad.Beckmann@amd.com 2808832SAli.Saidi@ARM.com /** This array is a per-sytem list of all devices capable of issuing a 2818832SAli.Saidi@ARM.com * memory system request and an associated string for each master id. 2828832SAli.Saidi@ARM.com * It's used to uniquely id any master in the system by name for things 2838832SAli.Saidi@ARM.com * like cache statistics. 2848832SAli.Saidi@ARM.com */ 2858832SAli.Saidi@ARM.com std::vector<std::string> masterIds; 2868832SAli.Saidi@ARM.com 2877914SBrad.Beckmann@amd.com public: 2888832SAli.Saidi@ARM.com 2898832SAli.Saidi@ARM.com /** Request an id used to create a request object in the system. All objects 2908832SAli.Saidi@ARM.com * that intend to issues requests into the memory system must request an id 2918832SAli.Saidi@ARM.com * in the init() phase of startup. All master ids must be fixed by the 2928832SAli.Saidi@ARM.com * regStats() phase that immediately preceeds it. This allows objects in the 2938832SAli.Saidi@ARM.com * memory system to understand how many masters may exist and 2948832SAli.Saidi@ARM.com * appropriately name the bins of their per-master stats before the stats 2958832SAli.Saidi@ARM.com * are finalized 2968832SAli.Saidi@ARM.com */ 2978832SAli.Saidi@ARM.com MasterID getMasterId(std::string req_name); 2988832SAli.Saidi@ARM.com 2998832SAli.Saidi@ARM.com /** Get the name of an object for a given request id. 3008832SAli.Saidi@ARM.com */ 3018832SAli.Saidi@ARM.com std::string getMasterName(MasterID master_id); 3028832SAli.Saidi@ARM.com 3038832SAli.Saidi@ARM.com /** Get the number of masters registered in the system */ 3048832SAli.Saidi@ARM.com MasterID maxMasters() 3058832SAli.Saidi@ARM.com { 3068832SAli.Saidi@ARM.com return masterIds.size(); 3078832SAli.Saidi@ARM.com } 3088832SAli.Saidi@ARM.com 3098666SPrakash.Ramrakhyani@arm.com virtual void regStats(); 3107914SBrad.Beckmann@amd.com /** 3117914SBrad.Beckmann@amd.com * Called by pseudo_inst to track the number of work items started by this 3127914SBrad.Beckmann@amd.com * system. 3137914SBrad.Beckmann@amd.com */ 3148666SPrakash.Ramrakhyani@arm.com uint64_t 3157914SBrad.Beckmann@amd.com incWorkItemsBegin() 3167914SBrad.Beckmann@amd.com { 3177914SBrad.Beckmann@amd.com return ++workItemsBegin; 3187914SBrad.Beckmann@amd.com } 3197914SBrad.Beckmann@amd.com 3207914SBrad.Beckmann@amd.com /** 3217914SBrad.Beckmann@amd.com * Called by pseudo_inst to track the number of work items completed by 3227914SBrad.Beckmann@amd.com * this system. 3237914SBrad.Beckmann@amd.com */ 3247914SBrad.Beckmann@amd.com uint64_t 3257914SBrad.Beckmann@amd.com incWorkItemsEnd() 3267914SBrad.Beckmann@amd.com { 3277914SBrad.Beckmann@amd.com return ++workItemsEnd; 3287914SBrad.Beckmann@amd.com } 3297914SBrad.Beckmann@amd.com 3307914SBrad.Beckmann@amd.com /** 3317914SBrad.Beckmann@amd.com * Called by pseudo_inst to mark the cpus actively executing work items. 3327914SBrad.Beckmann@amd.com * Returns the total number of cpus that have executed work item begin or 3337914SBrad.Beckmann@amd.com * ends. 3347914SBrad.Beckmann@amd.com */ 3357914SBrad.Beckmann@amd.com int 3367914SBrad.Beckmann@amd.com markWorkItem(int index) 3377914SBrad.Beckmann@amd.com { 3387914SBrad.Beckmann@amd.com int count = 0; 3397914SBrad.Beckmann@amd.com assert(index < activeCpus.size()); 3407914SBrad.Beckmann@amd.com activeCpus[index] = true; 3417914SBrad.Beckmann@amd.com for (std::vector<bool>::iterator i = activeCpus.begin(); 3427914SBrad.Beckmann@amd.com i < activeCpus.end(); i++) { 3437914SBrad.Beckmann@amd.com if (*i) count++; 3447914SBrad.Beckmann@amd.com } 3457914SBrad.Beckmann@amd.com return count; 3467914SBrad.Beckmann@amd.com } 3472901Ssaidi@eecs.umich.edu 3488666SPrakash.Ramrakhyani@arm.com inline void workItemBegin(uint32_t tid, uint32_t workid) 3498666SPrakash.Ramrakhyani@arm.com { 3508666SPrakash.Ramrakhyani@arm.com std::pair<uint32_t,uint32_t> p(tid, workid); 3518666SPrakash.Ramrakhyani@arm.com lastWorkItemStarted[p] = curTick(); 3528666SPrakash.Ramrakhyani@arm.com } 3538666SPrakash.Ramrakhyani@arm.com 3548666SPrakash.Ramrakhyani@arm.com void workItemEnd(uint32_t tid, uint32_t workid); 3558666SPrakash.Ramrakhyani@arm.com 3561885SN/A /** 3571885SN/A * Fix up an address used to match PCs for hooking simulator 3581885SN/A * events on to target function executions. See comment in 3591885SN/A * system.cc for details. 3601885SN/A */ 3618769Sgblack@eecs.umich.edu virtual Addr fixFuncEventAddr(Addr addr) 3628769Sgblack@eecs.umich.edu { 3638769Sgblack@eecs.umich.edu panic("Base fixFuncEventAddr not implemented.\n"); 3648769Sgblack@eecs.umich.edu } 3651885SN/A 3669645SAndreas.Sandberg@ARM.com /** @{ */ 3671885SN/A /** 3681885SN/A * Add a function-based event to the given function, to be looked 3691885SN/A * up in the specified symbol table. 3709645SAndreas.Sandberg@ARM.com * 3719645SAndreas.Sandberg@ARM.com * The ...OrPanic flavor of the method causes the simulator to 3729645SAndreas.Sandberg@ARM.com * panic if the symbol can't be found. 3739645SAndreas.Sandberg@ARM.com * 3749645SAndreas.Sandberg@ARM.com * @param symtab Symbol table to use for look up. 3759645SAndreas.Sandberg@ARM.com * @param lbl Function to hook the event to. 3769645SAndreas.Sandberg@ARM.com * @param desc Description to be passed to the event. 3779645SAndreas.Sandberg@ARM.com * @param args Arguments to be forwarded to the event constructor. 3781885SN/A */ 3799645SAndreas.Sandberg@ARM.com template <class T, typename... Args> 3809645SAndreas.Sandberg@ARM.com T *addFuncEvent(const SymbolTable *symtab, const char *lbl, 3819645SAndreas.Sandberg@ARM.com const std::string &desc, Args... args) 3821885SN/A { 3831913SN/A Addr addr = 0; // initialize only to avoid compiler warning 3841885SN/A 3859850Sandreas.hansson@arm.com#if THE_ISA != NULL_ISA 3861885SN/A if (symtab->findAddress(lbl, addr)) { 3879645SAndreas.Sandberg@ARM.com T *ev = new T(&pcEventQueue, desc, fixFuncEventAddr(addr), 3889645SAndreas.Sandberg@ARM.com std::forward<Args>(args)...); 3891885SN/A return ev; 3901885SN/A } 3919850Sandreas.hansson@arm.com#endif 3921885SN/A 3931885SN/A return NULL; 3941885SN/A } 3951885SN/A 3961885SN/A template <class T> 3979645SAndreas.Sandberg@ARM.com T *addFuncEvent(const SymbolTable *symtab, const char *lbl) 3981885SN/A { 3999645SAndreas.Sandberg@ARM.com return addFuncEvent<T>(symtab, lbl, lbl); 4001885SN/A } 4011885SN/A 4029645SAndreas.Sandberg@ARM.com template <class T, typename... Args> 4039645SAndreas.Sandberg@ARM.com T *addFuncEventOrPanic(const SymbolTable *symtab, const char *lbl, 4049645SAndreas.Sandberg@ARM.com Args... args) 4059645SAndreas.Sandberg@ARM.com { 4069645SAndreas.Sandberg@ARM.com T *e(addFuncEvent<T>(symtab, lbl, std::forward<Args>(args)...)); 4079645SAndreas.Sandberg@ARM.com if (!e) 4089645SAndreas.Sandberg@ARM.com panic("Failed to find symbol '%s'", lbl); 4099645SAndreas.Sandberg@ARM.com return e; 4109645SAndreas.Sandberg@ARM.com } 4119645SAndreas.Sandberg@ARM.com /** @} */ 4129645SAndreas.Sandberg@ARM.com 4139645SAndreas.Sandberg@ARM.com /** @{ */ 4149645SAndreas.Sandberg@ARM.com /** 4159645SAndreas.Sandberg@ARM.com * Add a function-based event to a kernel symbol. 4169645SAndreas.Sandberg@ARM.com * 4179645SAndreas.Sandberg@ARM.com * These functions work like their addFuncEvent() and 4189645SAndreas.Sandberg@ARM.com * addFuncEventOrPanic() counterparts. The only difference is that 4199645SAndreas.Sandberg@ARM.com * they automatically use the kernel symbol table. All arguments 4209645SAndreas.Sandberg@ARM.com * are forwarded to the underlying method. 4219645SAndreas.Sandberg@ARM.com * 4229645SAndreas.Sandberg@ARM.com * @see addFuncEvent() 4239645SAndreas.Sandberg@ARM.com * @see addFuncEventOrPanic() 4249645SAndreas.Sandberg@ARM.com * 4259645SAndreas.Sandberg@ARM.com * @param lbl Function to hook the event to. 4269645SAndreas.Sandberg@ARM.com * @param args Arguments to be passed to addFuncEvent 4279645SAndreas.Sandberg@ARM.com */ 4289645SAndreas.Sandberg@ARM.com template <class T, typename... Args> 4299645SAndreas.Sandberg@ARM.com T *addKernelFuncEvent(const char *lbl, Args... args) 4309645SAndreas.Sandberg@ARM.com { 4319645SAndreas.Sandberg@ARM.com return addFuncEvent<T>(kernelSymtab, lbl, 4329645SAndreas.Sandberg@ARM.com std::forward<Args>(args)...); 4339645SAndreas.Sandberg@ARM.com } 4349645SAndreas.Sandberg@ARM.com 4359645SAndreas.Sandberg@ARM.com template <class T, typename... Args> 4369645SAndreas.Sandberg@ARM.com T *addKernelFuncEventOrPanic(const char *lbl, Args... args) 4379645SAndreas.Sandberg@ARM.com { 4389645SAndreas.Sandberg@ARM.com T *e(addFuncEvent<T>(kernelSymtab, lbl, 4399645SAndreas.Sandberg@ARM.com std::forward<Args>(args)...)); 4409645SAndreas.Sandberg@ARM.com if (!e) 4419645SAndreas.Sandberg@ARM.com panic("Failed to find kernel symbol '%s'", lbl); 4429645SAndreas.Sandberg@ARM.com return e; 4439645SAndreas.Sandberg@ARM.com } 4449645SAndreas.Sandberg@ARM.com /** @} */ 4459645SAndreas.Sandberg@ARM.com 44677SN/A public: 4476658Snate@binkert.org std::vector<BaseRemoteGDB *> remoteGDB; 4481070SN/A std::vector<GDBListener *> gdbListen; 4493960Sgblack@eecs.umich.edu bool breakpoint(); 4501070SN/A 4511070SN/A public: 4524762Snate@binkert.org typedef SystemParams Params; 4531070SN/A 4542158SN/A protected: 4552158SN/A Params *_params; 4561070SN/A 4572158SN/A public: 4581070SN/A System(Params *p); 4592SN/A ~System(); 4602SN/A 4617733SAli.Saidi@ARM.com void initState(); 4621129SN/A 4632158SN/A const Params *params() const { return (const Params *)_params; } 4642158SN/A 4651070SN/A public: 4662378SN/A 4671070SN/A /** 4681070SN/A * Returns the addess the kernel starts at. 4691070SN/A * @return address the kernel starts at 4701070SN/A */ 4711070SN/A Addr getKernelStart() const { return kernelStart; } 4721070SN/A 4731070SN/A /** 4741070SN/A * Returns the addess the kernel ends at. 4751070SN/A * @return address the kernel ends at 4761070SN/A */ 4771070SN/A Addr getKernelEnd() const { return kernelEnd; } 4781070SN/A 4791070SN/A /** 4801070SN/A * Returns the addess the entry point to the kernel code. 4811070SN/A * @return entry point of the kernel code 4821070SN/A */ 4831070SN/A Addr getKernelEntry() const { return kernelEntry; } 4841070SN/A 4858601Ssteve.reinhardt@amd.com /// Allocate npages contiguous unused physical pages 4868601Ssteve.reinhardt@amd.com /// @return Starting address of first page 4878601Ssteve.reinhardt@amd.com Addr allocPhysPages(int npages); 4882378SN/A 4895718Shsul@eecs.umich.edu int registerThreadContext(ThreadContext *tc, int assigned=-1); 4905713Shsul@eecs.umich.edu void replaceThreadContext(ThreadContext *tc, int context_id); 4911070SN/A 4921070SN/A void serialize(std::ostream &os); 4931070SN/A void unserialize(Checkpoint *cp, const std::string §ion); 4949342SAndreas.Sandberg@arm.com 4959342SAndreas.Sandberg@arm.com unsigned int drain(DrainManager *dm); 4969342SAndreas.Sandberg@arm.com void drainResume(); 4972SN/A 49877SN/A public: 4997897Shestness@cs.utexas.edu Counter totalNumInsts; 5007897Shestness@cs.utexas.edu EventQueue instEventQueue; 5018666SPrakash.Ramrakhyani@arm.com std::map<std::pair<uint32_t,uint32_t>, Tick> lastWorkItemStarted; 5028666SPrakash.Ramrakhyani@arm.com std::map<uint32_t, Stats::Histogram*> workItemStats; 5037897Shestness@cs.utexas.edu 5042SN/A //////////////////////////////////////////// 5052SN/A // 5062SN/A // STATIC GLOBAL SYSTEM LIST 5072SN/A // 5082SN/A //////////////////////////////////////////// 5092SN/A 5102SN/A static std::vector<System *> systemList; 5112SN/A static int numSystemsRunning; 5122SN/A 5132SN/A static void printSystems(); 5142158SN/A 5159112Smarc.orr@gmail.com // For futex system call 5169112Smarc.orr@gmail.com std::map<uint64_t, std::list<ThreadContext *> * > futexMap; 5179112Smarc.orr@gmail.com 5189292Sandreas.hansson@arm.com protected: 5199292Sandreas.hansson@arm.com 5209292Sandreas.hansson@arm.com /** 5219292Sandreas.hansson@arm.com * If needed, serialize additional symbol table entries for a 5229292Sandreas.hansson@arm.com * specific subclass of this sytem. Currently this is used by 5239292Sandreas.hansson@arm.com * Alpha and MIPS. 5249292Sandreas.hansson@arm.com * 5259292Sandreas.hansson@arm.com * @param os stream to serialize to 5269292Sandreas.hansson@arm.com */ 5279292Sandreas.hansson@arm.com virtual void serializeSymtab(std::ostream &os) {} 5289292Sandreas.hansson@arm.com 5299292Sandreas.hansson@arm.com /** 5309292Sandreas.hansson@arm.com * If needed, unserialize additional symbol table entries for a 5319292Sandreas.hansson@arm.com * specific subclass of this system. 5329292Sandreas.hansson@arm.com * 5339292Sandreas.hansson@arm.com * @param cp checkpoint to unserialize from 5349292Sandreas.hansson@arm.com * @param section relevant section in the checkpoint 5359292Sandreas.hansson@arm.com */ 5369292Sandreas.hansson@arm.com virtual void unserializeSymtab(Checkpoint *cp, 5379292Sandreas.hansson@arm.com const std::string §ion) {} 5382158SN/A 5392SN/A}; 5402SN/A 5419554Sandreas.hansson@arm.comvoid printSystems(); 5429554Sandreas.hansson@arm.com 5432SN/A#endif // __SYSTEM_HH__ 544