system.hh revision 9554
12SN/A/* 28703Sandreas.hansson@arm.com * Copyright (c) 2012 ARM Limited 38703Sandreas.hansson@arm.com * All rights reserved 48703Sandreas.hansson@arm.com * 58703Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68703Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78703Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88703Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98703Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108703Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118703Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128703Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138703Sandreas.hansson@arm.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422665Ssaidi@eecs.umich.edu * Lisa Hsu 432665Ssaidi@eecs.umich.edu * Nathan Binkert 447897Shestness@cs.utexas.edu * Rick Strong 452SN/A */ 462SN/A 472SN/A#ifndef __SYSTEM_HH__ 482SN/A#define __SYSTEM_HH__ 492SN/A 502SN/A#include <string> 5175SN/A#include <vector> 522SN/A 532439SN/A#include "base/loader/symtab.hh" 542439SN/A#include "base/misc.hh" 55603SN/A#include "base/statistics.hh" 56603SN/A#include "cpu/pc_event.hh" 574762Snate@binkert.org#include "enums/MemoryMode.hh" 588769Sgblack@eecs.umich.edu#include "kern/system_events.hh" 598852Sandreas.hansson@arm.com#include "mem/fs_translating_port_proxy.hh" 608703Sandreas.hansson@arm.com#include "mem/mem_object.hh" 612520SN/A#include "mem/port.hh" 628931Sandreas.hansson@arm.com#include "mem/physical.hh" 634762Snate@binkert.org#include "params/System.hh" 646658Snate@binkert.org 651634SN/Aclass BaseCPU; 668769Sgblack@eecs.umich.educlass BaseRemoteGDB; 678769Sgblack@eecs.umich.educlass GDBListener; 681634SN/Aclass ObjectFile; 69803SN/Aclass Platform; 708769Sgblack@eecs.umich.educlass ThreadContext; 712SN/A 728703Sandreas.hansson@arm.comclass System : public MemObject 732SN/A{ 748703Sandreas.hansson@arm.com private: 758703Sandreas.hansson@arm.com 768703Sandreas.hansson@arm.com /** 778703Sandreas.hansson@arm.com * Private class for the system port which is only used as a 788703Sandreas.hansson@arm.com * master for debug access and for non-structural entities that do 798703Sandreas.hansson@arm.com * not have a port of their own. 808703Sandreas.hansson@arm.com */ 818922Swilliam.wang@arm.com class SystemPort : public MasterPort 828703Sandreas.hansson@arm.com { 838703Sandreas.hansson@arm.com public: 848703Sandreas.hansson@arm.com 858703Sandreas.hansson@arm.com /** 868703Sandreas.hansson@arm.com * Create a system port with a name and an owner. 878703Sandreas.hansson@arm.com */ 888703Sandreas.hansson@arm.com SystemPort(const std::string &_name, MemObject *_owner) 898922Swilliam.wang@arm.com : MasterPort(_name, _owner) 908703Sandreas.hansson@arm.com { } 918975Sandreas.hansson@arm.com bool recvTimingResp(PacketPtr pkt) 928703Sandreas.hansson@arm.com { panic("SystemPort does not receive timing!\n"); return false; } 938922Swilliam.wang@arm.com void recvRetry() 948922Swilliam.wang@arm.com { panic("SystemPort does not expect retry!\n"); } 958703Sandreas.hansson@arm.com }; 968703Sandreas.hansson@arm.com 978703Sandreas.hansson@arm.com SystemPort _systemPort; 988703Sandreas.hansson@arm.com 99603SN/A public: 1002901Ssaidi@eecs.umich.edu 1018703Sandreas.hansson@arm.com /** 1028706Sandreas.hansson@arm.com * After all objects have been created and all ports are 1038706Sandreas.hansson@arm.com * connected, check that the system port is connected. 1048706Sandreas.hansson@arm.com */ 1058706Sandreas.hansson@arm.com virtual void init(); 1068706Sandreas.hansson@arm.com 1078706Sandreas.hansson@arm.com /** 1088852Sandreas.hansson@arm.com * Get a reference to the system port that can be used by 1098703Sandreas.hansson@arm.com * non-structural simulation objects like processes or threads, or 1108703Sandreas.hansson@arm.com * external entities like loaders and debuggers, etc, to access 1118703Sandreas.hansson@arm.com * the memory system. 1128703Sandreas.hansson@arm.com * 1138852Sandreas.hansson@arm.com * @return a reference to the system port we own 1148703Sandreas.hansson@arm.com */ 1158922Swilliam.wang@arm.com MasterPort& getSystemPort() { return _systemPort; } 1168703Sandreas.hansson@arm.com 1178703Sandreas.hansson@arm.com /** 1188703Sandreas.hansson@arm.com * Additional function to return the Port of a memory object. 1198703Sandreas.hansson@arm.com */ 1209294Sandreas.hansson@arm.com BaseMasterPort& getMasterPort(const std::string &if_name, 1219294Sandreas.hansson@arm.com PortID idx = InvalidPortID); 1228703Sandreas.hansson@arm.com 1239524SAndreas.Sandberg@ARM.com static const char *MemoryModeStrings[4]; 1242902Ssaidi@eecs.umich.edu 1259524SAndreas.Sandberg@ARM.com /** @{ */ 1269524SAndreas.Sandberg@ARM.com /** 1279524SAndreas.Sandberg@ARM.com * Is the system in atomic mode? 1289524SAndreas.Sandberg@ARM.com * 1299524SAndreas.Sandberg@ARM.com * There are currently two different atomic memory modes: 1309524SAndreas.Sandberg@ARM.com * 'atomic', which supports caches; and 'atomic_noncaching', which 1319524SAndreas.Sandberg@ARM.com * bypasses caches. The latter is used by hardware virtualized 1329524SAndreas.Sandberg@ARM.com * CPUs. SimObjects are expected to use Port::sendAtomic() and 1339524SAndreas.Sandberg@ARM.com * Port::recvAtomic() when accessing memory in this mode. 1349524SAndreas.Sandberg@ARM.com */ 1359524SAndreas.Sandberg@ARM.com bool isAtomicMode() const { 1369524SAndreas.Sandberg@ARM.com return memoryMode == Enums::atomic || 1379524SAndreas.Sandberg@ARM.com memoryMode == Enums::atomic_noncaching; 1384762Snate@binkert.org } 1392901Ssaidi@eecs.umich.edu 1409524SAndreas.Sandberg@ARM.com /** 1419524SAndreas.Sandberg@ARM.com * Is the system in timing mode? 1429524SAndreas.Sandberg@ARM.com * 1439524SAndreas.Sandberg@ARM.com * SimObjects are expected to use Port::sendTiming() and 1449524SAndreas.Sandberg@ARM.com * Port::recvTiming() when accessing memory in this mode. 1459524SAndreas.Sandberg@ARM.com */ 1469524SAndreas.Sandberg@ARM.com bool isTimingMode() const { 1479524SAndreas.Sandberg@ARM.com return memoryMode == Enums::timing; 1489524SAndreas.Sandberg@ARM.com } 1499524SAndreas.Sandberg@ARM.com 1509524SAndreas.Sandberg@ARM.com /** 1519524SAndreas.Sandberg@ARM.com * Should caches be bypassed? 1529524SAndreas.Sandberg@ARM.com * 1539524SAndreas.Sandberg@ARM.com * Some CPUs need to bypass caches to allow direct memory 1549524SAndreas.Sandberg@ARM.com * accesses, which is required for hardware virtualization. 1559524SAndreas.Sandberg@ARM.com */ 1569524SAndreas.Sandberg@ARM.com bool bypassCaches() const { 1579524SAndreas.Sandberg@ARM.com return memoryMode == Enums::atomic_noncaching; 1589524SAndreas.Sandberg@ARM.com } 1599524SAndreas.Sandberg@ARM.com /** @} */ 1609524SAndreas.Sandberg@ARM.com 1619524SAndreas.Sandberg@ARM.com /** @{ */ 1629524SAndreas.Sandberg@ARM.com /** 1639524SAndreas.Sandberg@ARM.com * Get the memory mode of the system. 1649524SAndreas.Sandberg@ARM.com * 1659524SAndreas.Sandberg@ARM.com * \warn This should only be used by the Python world. The C++ 1669524SAndreas.Sandberg@ARM.com * world should use one of the query functions above 1679524SAndreas.Sandberg@ARM.com * (isAtomicMode(), isTimingMode(), bypassCaches()). 1689524SAndreas.Sandberg@ARM.com */ 1699524SAndreas.Sandberg@ARM.com Enums::MemoryMode getMemoryMode() const { return memoryMode; } 1709524SAndreas.Sandberg@ARM.com 1719524SAndreas.Sandberg@ARM.com /** 1729524SAndreas.Sandberg@ARM.com * Change the memory mode of the system. 1739524SAndreas.Sandberg@ARM.com * 1749524SAndreas.Sandberg@ARM.com * \warn This should only be called by the Python! 1759524SAndreas.Sandberg@ARM.com * 1769524SAndreas.Sandberg@ARM.com * @param mode Mode to change to (atomic/timing/...) 1772901Ssaidi@eecs.umich.edu */ 1784762Snate@binkert.org void setMemoryMode(Enums::MemoryMode mode); 1799524SAndreas.Sandberg@ARM.com /** @} */ 1802901Ssaidi@eecs.umich.edu 1812SN/A PCEventQueue pcEventQueue; 1822SN/A 1832680Sktlim@umich.edu std::vector<ThreadContext *> threadContexts; 1845714Shsul@eecs.umich.edu int _numContexts; 1851806SN/A 1866221Snate@binkert.org ThreadContext *getThreadContext(ThreadID tid) 1875713Shsul@eecs.umich.edu { 1885713Shsul@eecs.umich.edu return threadContexts[tid]; 1895713Shsul@eecs.umich.edu } 1905713Shsul@eecs.umich.edu 1915714Shsul@eecs.umich.edu int numContexts() 1921806SN/A { 1936227Snate@binkert.org assert(_numContexts == (int)threadContexts.size()); 1945714Shsul@eecs.umich.edu return _numContexts; 1951806SN/A } 196180SN/A 1976029Ssteve.reinhardt@amd.com /** Return number of running (non-halted) thread contexts in 1986029Ssteve.reinhardt@amd.com * system. These threads could be Active or Suspended. */ 1996029Ssteve.reinhardt@amd.com int numRunningContexts(); 2006029Ssteve.reinhardt@amd.com 2018765Sgblack@eecs.umich.edu Addr pagePtr; 2028765Sgblack@eecs.umich.edu 2032378SN/A uint64_t init_param; 2042378SN/A 2052520SN/A /** Port to physical memory used for writing object files into ram at 2062520SN/A * boot.*/ 2078852Sandreas.hansson@arm.com PortProxy physProxy; 2088852Sandreas.hansson@arm.com FSTranslatingPortProxy virtProxy; 2092520SN/A 2101885SN/A /** kernel symbol table */ 2111070SN/A SymbolTable *kernelSymtab; 212954SN/A 2131070SN/A /** Object pointer for the kernel code */ 2141070SN/A ObjectFile *kernel; 2151070SN/A 2161070SN/A /** Begining of kernel code */ 2171070SN/A Addr kernelStart; 2181070SN/A 2191070SN/A /** End of kernel code */ 2201070SN/A Addr kernelEnd; 2211070SN/A 2221070SN/A /** Entry point in the kernel to start at */ 2231070SN/A Addr kernelEntry; 2241070SN/A 2257580SAli.Saidi@arm.com /** Mask that should be anded for binary/symbol loading. 2267580SAli.Saidi@arm.com * This allows one two different OS requirements for the same ISA to be 2277580SAli.Saidi@arm.com * handled. Some OSes are compiled for a virtual address and need to be 2287580SAli.Saidi@arm.com * loaded into physical memory that starts at address 0, while other 2297580SAli.Saidi@arm.com * bare metal tools generate images that start at address 0. 2307580SAli.Saidi@arm.com */ 2317580SAli.Saidi@arm.com Addr loadAddrMask; 2327580SAli.Saidi@arm.com 2334997Sgblack@eecs.umich.edu protected: 2347770SAli.Saidi@ARM.com uint64_t nextPID; 2354997Sgblack@eecs.umich.edu 2364997Sgblack@eecs.umich.edu public: 2374997Sgblack@eecs.umich.edu uint64_t allocatePID() 2384997Sgblack@eecs.umich.edu { 2397770SAli.Saidi@ARM.com return nextPID++; 2404997Sgblack@eecs.umich.edu } 2414997Sgblack@eecs.umich.edu 2428931Sandreas.hansson@arm.com /** Get a pointer to access the physical memory of the system */ 2438931Sandreas.hansson@arm.com PhysicalMemory& getPhysMem() { return physmem; } 2448931Sandreas.hansson@arm.com 2455795Ssaidi@eecs.umich.edu /** Amount of physical memory that is still free */ 2468931Sandreas.hansson@arm.com Addr freeMemSize() const; 2475795Ssaidi@eecs.umich.edu 2485795Ssaidi@eecs.umich.edu /** Amount of physical memory that exists */ 2498931Sandreas.hansson@arm.com Addr memSize() const; 2508931Sandreas.hansson@arm.com 2518931Sandreas.hansson@arm.com /** 2528931Sandreas.hansson@arm.com * Check if a physical address is within a range of a memory that 2538931Sandreas.hansson@arm.com * is part of the global address map. 2548931Sandreas.hansson@arm.com * 2558931Sandreas.hansson@arm.com * @param addr A physical address 2568931Sandreas.hansson@arm.com * @return Whether the address corresponds to a memory 2578931Sandreas.hansson@arm.com */ 2588931Sandreas.hansson@arm.com bool isMemAddr(Addr addr) const; 2595795Ssaidi@eecs.umich.edu 2601885SN/A protected: 2618931Sandreas.hansson@arm.com 2628931Sandreas.hansson@arm.com PhysicalMemory physmem; 2638931Sandreas.hansson@arm.com 2644762Snate@binkert.org Enums::MemoryMode memoryMode; 2657914SBrad.Beckmann@amd.com uint64_t workItemsBegin; 2667914SBrad.Beckmann@amd.com uint64_t workItemsEnd; 2678666SPrakash.Ramrakhyani@arm.com uint32_t numWorkIds; 2687914SBrad.Beckmann@amd.com std::vector<bool> activeCpus; 2697914SBrad.Beckmann@amd.com 2708832SAli.Saidi@ARM.com /** This array is a per-sytem list of all devices capable of issuing a 2718832SAli.Saidi@ARM.com * memory system request and an associated string for each master id. 2728832SAli.Saidi@ARM.com * It's used to uniquely id any master in the system by name for things 2738832SAli.Saidi@ARM.com * like cache statistics. 2748832SAli.Saidi@ARM.com */ 2758832SAli.Saidi@ARM.com std::vector<std::string> masterIds; 2768832SAli.Saidi@ARM.com 2777914SBrad.Beckmann@amd.com public: 2788832SAli.Saidi@ARM.com 2798832SAli.Saidi@ARM.com /** Request an id used to create a request object in the system. All objects 2808832SAli.Saidi@ARM.com * that intend to issues requests into the memory system must request an id 2818832SAli.Saidi@ARM.com * in the init() phase of startup. All master ids must be fixed by the 2828832SAli.Saidi@ARM.com * regStats() phase that immediately preceeds it. This allows objects in the 2838832SAli.Saidi@ARM.com * memory system to understand how many masters may exist and 2848832SAli.Saidi@ARM.com * appropriately name the bins of their per-master stats before the stats 2858832SAli.Saidi@ARM.com * are finalized 2868832SAli.Saidi@ARM.com */ 2878832SAli.Saidi@ARM.com MasterID getMasterId(std::string req_name); 2888832SAli.Saidi@ARM.com 2898832SAli.Saidi@ARM.com /** Get the name of an object for a given request id. 2908832SAli.Saidi@ARM.com */ 2918832SAli.Saidi@ARM.com std::string getMasterName(MasterID master_id); 2928832SAli.Saidi@ARM.com 2938832SAli.Saidi@ARM.com /** Get the number of masters registered in the system */ 2948832SAli.Saidi@ARM.com MasterID maxMasters() 2958832SAli.Saidi@ARM.com { 2968832SAli.Saidi@ARM.com return masterIds.size(); 2978832SAli.Saidi@ARM.com } 2988832SAli.Saidi@ARM.com 2998666SPrakash.Ramrakhyani@arm.com virtual void regStats(); 3007914SBrad.Beckmann@amd.com /** 3017914SBrad.Beckmann@amd.com * Called by pseudo_inst to track the number of work items started by this 3027914SBrad.Beckmann@amd.com * system. 3037914SBrad.Beckmann@amd.com */ 3048666SPrakash.Ramrakhyani@arm.com uint64_t 3057914SBrad.Beckmann@amd.com incWorkItemsBegin() 3067914SBrad.Beckmann@amd.com { 3077914SBrad.Beckmann@amd.com return ++workItemsBegin; 3087914SBrad.Beckmann@amd.com } 3097914SBrad.Beckmann@amd.com 3107914SBrad.Beckmann@amd.com /** 3117914SBrad.Beckmann@amd.com * Called by pseudo_inst to track the number of work items completed by 3127914SBrad.Beckmann@amd.com * this system. 3137914SBrad.Beckmann@amd.com */ 3147914SBrad.Beckmann@amd.com uint64_t 3157914SBrad.Beckmann@amd.com incWorkItemsEnd() 3167914SBrad.Beckmann@amd.com { 3177914SBrad.Beckmann@amd.com return ++workItemsEnd; 3187914SBrad.Beckmann@amd.com } 3197914SBrad.Beckmann@amd.com 3207914SBrad.Beckmann@amd.com /** 3217914SBrad.Beckmann@amd.com * Called by pseudo_inst to mark the cpus actively executing work items. 3227914SBrad.Beckmann@amd.com * Returns the total number of cpus that have executed work item begin or 3237914SBrad.Beckmann@amd.com * ends. 3247914SBrad.Beckmann@amd.com */ 3257914SBrad.Beckmann@amd.com int 3267914SBrad.Beckmann@amd.com markWorkItem(int index) 3277914SBrad.Beckmann@amd.com { 3287914SBrad.Beckmann@amd.com int count = 0; 3297914SBrad.Beckmann@amd.com assert(index < activeCpus.size()); 3307914SBrad.Beckmann@amd.com activeCpus[index] = true; 3317914SBrad.Beckmann@amd.com for (std::vector<bool>::iterator i = activeCpus.begin(); 3327914SBrad.Beckmann@amd.com i < activeCpus.end(); i++) { 3337914SBrad.Beckmann@amd.com if (*i) count++; 3347914SBrad.Beckmann@amd.com } 3357914SBrad.Beckmann@amd.com return count; 3367914SBrad.Beckmann@amd.com } 3372901Ssaidi@eecs.umich.edu 3388666SPrakash.Ramrakhyani@arm.com inline void workItemBegin(uint32_t tid, uint32_t workid) 3398666SPrakash.Ramrakhyani@arm.com { 3408666SPrakash.Ramrakhyani@arm.com std::pair<uint32_t,uint32_t> p(tid, workid); 3418666SPrakash.Ramrakhyani@arm.com lastWorkItemStarted[p] = curTick(); 3428666SPrakash.Ramrakhyani@arm.com } 3438666SPrakash.Ramrakhyani@arm.com 3448666SPrakash.Ramrakhyani@arm.com void workItemEnd(uint32_t tid, uint32_t workid); 3458666SPrakash.Ramrakhyani@arm.com 3461885SN/A /** 3471885SN/A * Fix up an address used to match PCs for hooking simulator 3481885SN/A * events on to target function executions. See comment in 3491885SN/A * system.cc for details. 3501885SN/A */ 3518769Sgblack@eecs.umich.edu virtual Addr fixFuncEventAddr(Addr addr) 3528769Sgblack@eecs.umich.edu { 3538769Sgblack@eecs.umich.edu panic("Base fixFuncEventAddr not implemented.\n"); 3548769Sgblack@eecs.umich.edu } 3551885SN/A 3561885SN/A /** 3571885SN/A * Add a function-based event to the given function, to be looked 3581885SN/A * up in the specified symbol table. 3591885SN/A */ 3601885SN/A template <class T> 3612989Ssaidi@eecs.umich.edu T *addFuncEvent(SymbolTable *symtab, const char *lbl) 3621885SN/A { 3631913SN/A Addr addr = 0; // initialize only to avoid compiler warning 3641885SN/A 3651885SN/A if (symtab->findAddress(lbl, addr)) { 3661885SN/A T *ev = new T(&pcEventQueue, lbl, fixFuncEventAddr(addr)); 3671885SN/A return ev; 3681885SN/A } 3691885SN/A 3701885SN/A return NULL; 3711885SN/A } 3721885SN/A 3731885SN/A /** Add a function-based event to kernel code. */ 3741885SN/A template <class T> 3752989Ssaidi@eecs.umich.edu T *addKernelFuncEvent(const char *lbl) 3761885SN/A { 3771885SN/A return addFuncEvent<T>(kernelSymtab, lbl); 3781885SN/A } 3791885SN/A 38077SN/A public: 3816658Snate@binkert.org std::vector<BaseRemoteGDB *> remoteGDB; 3821070SN/A std::vector<GDBListener *> gdbListen; 3833960Sgblack@eecs.umich.edu bool breakpoint(); 3841070SN/A 3851070SN/A public: 3864762Snate@binkert.org typedef SystemParams Params; 3871070SN/A 3882158SN/A protected: 3892158SN/A Params *_params; 3901070SN/A 3912158SN/A public: 3921070SN/A System(Params *p); 3932SN/A ~System(); 3942SN/A 3957733SAli.Saidi@ARM.com void initState(); 3961129SN/A 3972158SN/A const Params *params() const { return (const Params *)_params; } 3982158SN/A 3991070SN/A public: 4002378SN/A 4011070SN/A /** 4021070SN/A * Returns the addess the kernel starts at. 4031070SN/A * @return address the kernel starts at 4041070SN/A */ 4051070SN/A Addr getKernelStart() const { return kernelStart; } 4061070SN/A 4071070SN/A /** 4081070SN/A * Returns the addess the kernel ends at. 4091070SN/A * @return address the kernel ends at 4101070SN/A */ 4111070SN/A Addr getKernelEnd() const { return kernelEnd; } 4121070SN/A 4131070SN/A /** 4141070SN/A * Returns the addess the entry point to the kernel code. 4151070SN/A * @return entry point of the kernel code 4161070SN/A */ 4171070SN/A Addr getKernelEntry() const { return kernelEntry; } 4181070SN/A 4198601Ssteve.reinhardt@amd.com /// Allocate npages contiguous unused physical pages 4208601Ssteve.reinhardt@amd.com /// @return Starting address of first page 4218601Ssteve.reinhardt@amd.com Addr allocPhysPages(int npages); 4222378SN/A 4235718Shsul@eecs.umich.edu int registerThreadContext(ThreadContext *tc, int assigned=-1); 4245713Shsul@eecs.umich.edu void replaceThreadContext(ThreadContext *tc, int context_id); 4251070SN/A 4261070SN/A void serialize(std::ostream &os); 4271070SN/A void unserialize(Checkpoint *cp, const std::string §ion); 4289342SAndreas.Sandberg@arm.com 4299342SAndreas.Sandberg@arm.com unsigned int drain(DrainManager *dm); 4309342SAndreas.Sandberg@arm.com void drainResume(); 4312SN/A 43277SN/A public: 4337897Shestness@cs.utexas.edu Counter totalNumInsts; 4347897Shestness@cs.utexas.edu EventQueue instEventQueue; 4358666SPrakash.Ramrakhyani@arm.com std::map<std::pair<uint32_t,uint32_t>, Tick> lastWorkItemStarted; 4368666SPrakash.Ramrakhyani@arm.com std::map<uint32_t, Stats::Histogram*> workItemStats; 4377897Shestness@cs.utexas.edu 4382SN/A //////////////////////////////////////////// 4392SN/A // 4402SN/A // STATIC GLOBAL SYSTEM LIST 4412SN/A // 4422SN/A //////////////////////////////////////////// 4432SN/A 4442SN/A static std::vector<System *> systemList; 4452SN/A static int numSystemsRunning; 4462SN/A 4472SN/A static void printSystems(); 4482158SN/A 4499112Smarc.orr@gmail.com // For futex system call 4509112Smarc.orr@gmail.com std::map<uint64_t, std::list<ThreadContext *> * > futexMap; 4519112Smarc.orr@gmail.com 4529292Sandreas.hansson@arm.com protected: 4539292Sandreas.hansson@arm.com 4549292Sandreas.hansson@arm.com /** 4559292Sandreas.hansson@arm.com * If needed, serialize additional symbol table entries for a 4569292Sandreas.hansson@arm.com * specific subclass of this sytem. Currently this is used by 4579292Sandreas.hansson@arm.com * Alpha and MIPS. 4589292Sandreas.hansson@arm.com * 4599292Sandreas.hansson@arm.com * @param os stream to serialize to 4609292Sandreas.hansson@arm.com */ 4619292Sandreas.hansson@arm.com virtual void serializeSymtab(std::ostream &os) {} 4629292Sandreas.hansson@arm.com 4639292Sandreas.hansson@arm.com /** 4649292Sandreas.hansson@arm.com * If needed, unserialize additional symbol table entries for a 4659292Sandreas.hansson@arm.com * specific subclass of this system. 4669292Sandreas.hansson@arm.com * 4679292Sandreas.hansson@arm.com * @param cp checkpoint to unserialize from 4689292Sandreas.hansson@arm.com * @param section relevant section in the checkpoint 4699292Sandreas.hansson@arm.com */ 4709292Sandreas.hansson@arm.com virtual void unserializeSymtab(Checkpoint *cp, 4719292Sandreas.hansson@arm.com const std::string §ion) {} 4722158SN/A 4732SN/A}; 4742SN/A 4759554Sandreas.hansson@arm.comvoid printSystems(); 4769554Sandreas.hansson@arm.com 4772SN/A#endif // __SYSTEM_HH__ 478