system.hh revision 9112
12SN/A/* 28703Sandreas.hansson@arm.com * Copyright (c) 2012 ARM Limited 38703Sandreas.hansson@arm.com * All rights reserved 48703Sandreas.hansson@arm.com * 58703Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68703Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78703Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88703Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98703Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108703Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118703Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128703Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138703Sandreas.hansson@arm.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422665Ssaidi@eecs.umich.edu * Lisa Hsu 432665Ssaidi@eecs.umich.edu * Nathan Binkert 447897Shestness@cs.utexas.edu * Rick Strong 452SN/A */ 462SN/A 472SN/A#ifndef __SYSTEM_HH__ 482SN/A#define __SYSTEM_HH__ 492SN/A 502SN/A#include <string> 5175SN/A#include <vector> 522SN/A 532439SN/A#include "base/loader/symtab.hh" 542439SN/A#include "base/misc.hh" 55603SN/A#include "base/statistics.hh" 56603SN/A#include "cpu/pc_event.hh" 574762Snate@binkert.org#include "enums/MemoryMode.hh" 588769Sgblack@eecs.umich.edu#include "kern/system_events.hh" 598852Sandreas.hansson@arm.com#include "mem/fs_translating_port_proxy.hh" 608703Sandreas.hansson@arm.com#include "mem/mem_object.hh" 612520SN/A#include "mem/port.hh" 628931Sandreas.hansson@arm.com#include "mem/physical.hh" 634762Snate@binkert.org#include "params/System.hh" 646658Snate@binkert.org 651634SN/Aclass BaseCPU; 668769Sgblack@eecs.umich.educlass BaseRemoteGDB; 678769Sgblack@eecs.umich.educlass GDBListener; 681634SN/Aclass ObjectFile; 69803SN/Aclass Platform; 708769Sgblack@eecs.umich.educlass ThreadContext; 712SN/A 728703Sandreas.hansson@arm.comclass System : public MemObject 732SN/A{ 748703Sandreas.hansson@arm.com private: 758703Sandreas.hansson@arm.com 768703Sandreas.hansson@arm.com /** 778703Sandreas.hansson@arm.com * Private class for the system port which is only used as a 788703Sandreas.hansson@arm.com * master for debug access and for non-structural entities that do 798703Sandreas.hansson@arm.com * not have a port of their own. 808703Sandreas.hansson@arm.com */ 818922Swilliam.wang@arm.com class SystemPort : public MasterPort 828703Sandreas.hansson@arm.com { 838703Sandreas.hansson@arm.com public: 848703Sandreas.hansson@arm.com 858703Sandreas.hansson@arm.com /** 868703Sandreas.hansson@arm.com * Create a system port with a name and an owner. 878703Sandreas.hansson@arm.com */ 888703Sandreas.hansson@arm.com SystemPort(const std::string &_name, MemObject *_owner) 898922Swilliam.wang@arm.com : MasterPort(_name, _owner) 908703Sandreas.hansson@arm.com { } 918975Sandreas.hansson@arm.com bool recvTimingResp(PacketPtr pkt) 928703Sandreas.hansson@arm.com { panic("SystemPort does not receive timing!\n"); return false; } 938922Swilliam.wang@arm.com void recvRetry() 948922Swilliam.wang@arm.com { panic("SystemPort does not expect retry!\n"); } 958703Sandreas.hansson@arm.com }; 968703Sandreas.hansson@arm.com 978703Sandreas.hansson@arm.com SystemPort _systemPort; 988703Sandreas.hansson@arm.com 99603SN/A public: 1002901Ssaidi@eecs.umich.edu 1018703Sandreas.hansson@arm.com /** 1028706Sandreas.hansson@arm.com * After all objects have been created and all ports are 1038706Sandreas.hansson@arm.com * connected, check that the system port is connected. 1048706Sandreas.hansson@arm.com */ 1058706Sandreas.hansson@arm.com virtual void init(); 1068706Sandreas.hansson@arm.com 1078706Sandreas.hansson@arm.com /** 1088852Sandreas.hansson@arm.com * Get a reference to the system port that can be used by 1098703Sandreas.hansson@arm.com * non-structural simulation objects like processes or threads, or 1108703Sandreas.hansson@arm.com * external entities like loaders and debuggers, etc, to access 1118703Sandreas.hansson@arm.com * the memory system. 1128703Sandreas.hansson@arm.com * 1138852Sandreas.hansson@arm.com * @return a reference to the system port we own 1148703Sandreas.hansson@arm.com */ 1158922Swilliam.wang@arm.com MasterPort& getSystemPort() { return _systemPort; } 1168703Sandreas.hansson@arm.com 1178703Sandreas.hansson@arm.com /** 1188703Sandreas.hansson@arm.com * Additional function to return the Port of a memory object. 1198703Sandreas.hansson@arm.com */ 1208922Swilliam.wang@arm.com MasterPort& getMasterPort(const std::string &if_name, int idx = -1); 1218703Sandreas.hansson@arm.com 1222902Ssaidi@eecs.umich.edu static const char *MemoryModeStrings[3]; 1232902Ssaidi@eecs.umich.edu 1244762Snate@binkert.org Enums::MemoryMode 1254762Snate@binkert.org getMemoryMode() 1264762Snate@binkert.org { 1274762Snate@binkert.org assert(memoryMode); 1284762Snate@binkert.org return memoryMode; 1294762Snate@binkert.org } 1302901Ssaidi@eecs.umich.edu 1312901Ssaidi@eecs.umich.edu /** Change the memory mode of the system. This should only be called by the 1322901Ssaidi@eecs.umich.edu * python!! 1332901Ssaidi@eecs.umich.edu * @param mode Mode to change to (atomic/timing) 1342901Ssaidi@eecs.umich.edu */ 1354762Snate@binkert.org void setMemoryMode(Enums::MemoryMode mode); 1362901Ssaidi@eecs.umich.edu 1372SN/A PCEventQueue pcEventQueue; 1382SN/A 1392680Sktlim@umich.edu std::vector<ThreadContext *> threadContexts; 1405714Shsul@eecs.umich.edu int _numContexts; 1411806SN/A 1426221Snate@binkert.org ThreadContext *getThreadContext(ThreadID tid) 1435713Shsul@eecs.umich.edu { 1445713Shsul@eecs.umich.edu return threadContexts[tid]; 1455713Shsul@eecs.umich.edu } 1465713Shsul@eecs.umich.edu 1475714Shsul@eecs.umich.edu int numContexts() 1481806SN/A { 1496227Snate@binkert.org assert(_numContexts == (int)threadContexts.size()); 1505714Shsul@eecs.umich.edu return _numContexts; 1511806SN/A } 152180SN/A 1536029Ssteve.reinhardt@amd.com /** Return number of running (non-halted) thread contexts in 1546029Ssteve.reinhardt@amd.com * system. These threads could be Active or Suspended. */ 1556029Ssteve.reinhardt@amd.com int numRunningContexts(); 1566029Ssteve.reinhardt@amd.com 1578765Sgblack@eecs.umich.edu Addr pagePtr; 1588765Sgblack@eecs.umich.edu 1592378SN/A uint64_t init_param; 1602378SN/A 1612520SN/A /** Port to physical memory used for writing object files into ram at 1622520SN/A * boot.*/ 1638852Sandreas.hansson@arm.com PortProxy physProxy; 1648852Sandreas.hansson@arm.com FSTranslatingPortProxy virtProxy; 1652520SN/A 1661885SN/A /** kernel symbol table */ 1671070SN/A SymbolTable *kernelSymtab; 168954SN/A 1691070SN/A /** Object pointer for the kernel code */ 1701070SN/A ObjectFile *kernel; 1711070SN/A 1721070SN/A /** Begining of kernel code */ 1731070SN/A Addr kernelStart; 1741070SN/A 1751070SN/A /** End of kernel code */ 1761070SN/A Addr kernelEnd; 1771070SN/A 1781070SN/A /** Entry point in the kernel to start at */ 1791070SN/A Addr kernelEntry; 1801070SN/A 1817580SAli.Saidi@arm.com /** Mask that should be anded for binary/symbol loading. 1827580SAli.Saidi@arm.com * This allows one two different OS requirements for the same ISA to be 1837580SAli.Saidi@arm.com * handled. Some OSes are compiled for a virtual address and need to be 1847580SAli.Saidi@arm.com * loaded into physical memory that starts at address 0, while other 1857580SAli.Saidi@arm.com * bare metal tools generate images that start at address 0. 1867580SAli.Saidi@arm.com */ 1877580SAli.Saidi@arm.com Addr loadAddrMask; 1887580SAli.Saidi@arm.com 1894997Sgblack@eecs.umich.edu protected: 1907770SAli.Saidi@ARM.com uint64_t nextPID; 1914997Sgblack@eecs.umich.edu 1924997Sgblack@eecs.umich.edu public: 1934997Sgblack@eecs.umich.edu uint64_t allocatePID() 1944997Sgblack@eecs.umich.edu { 1957770SAli.Saidi@ARM.com return nextPID++; 1964997Sgblack@eecs.umich.edu } 1974997Sgblack@eecs.umich.edu 1988931Sandreas.hansson@arm.com /** Get a pointer to access the physical memory of the system */ 1998931Sandreas.hansson@arm.com PhysicalMemory& getPhysMem() { return physmem; } 2008931Sandreas.hansson@arm.com 2015795Ssaidi@eecs.umich.edu /** Amount of physical memory that is still free */ 2028931Sandreas.hansson@arm.com Addr freeMemSize() const; 2035795Ssaidi@eecs.umich.edu 2045795Ssaidi@eecs.umich.edu /** Amount of physical memory that exists */ 2058931Sandreas.hansson@arm.com Addr memSize() const; 2068931Sandreas.hansson@arm.com 2078931Sandreas.hansson@arm.com /** 2088931Sandreas.hansson@arm.com * Check if a physical address is within a range of a memory that 2098931Sandreas.hansson@arm.com * is part of the global address map. 2108931Sandreas.hansson@arm.com * 2118931Sandreas.hansson@arm.com * @param addr A physical address 2128931Sandreas.hansson@arm.com * @return Whether the address corresponds to a memory 2138931Sandreas.hansson@arm.com */ 2148931Sandreas.hansson@arm.com bool isMemAddr(Addr addr) const; 2155795Ssaidi@eecs.umich.edu 2161885SN/A protected: 2178931Sandreas.hansson@arm.com 2188931Sandreas.hansson@arm.com PhysicalMemory physmem; 2198931Sandreas.hansson@arm.com 2204762Snate@binkert.org Enums::MemoryMode memoryMode; 2217914SBrad.Beckmann@amd.com uint64_t workItemsBegin; 2227914SBrad.Beckmann@amd.com uint64_t workItemsEnd; 2238666SPrakash.Ramrakhyani@arm.com uint32_t numWorkIds; 2247914SBrad.Beckmann@amd.com std::vector<bool> activeCpus; 2257914SBrad.Beckmann@amd.com 2268832SAli.Saidi@ARM.com /** This array is a per-sytem list of all devices capable of issuing a 2278832SAli.Saidi@ARM.com * memory system request and an associated string for each master id. 2288832SAli.Saidi@ARM.com * It's used to uniquely id any master in the system by name for things 2298832SAli.Saidi@ARM.com * like cache statistics. 2308832SAli.Saidi@ARM.com */ 2318832SAli.Saidi@ARM.com std::vector<std::string> masterIds; 2328832SAli.Saidi@ARM.com 2337914SBrad.Beckmann@amd.com public: 2348832SAli.Saidi@ARM.com 2358832SAli.Saidi@ARM.com /** Request an id used to create a request object in the system. All objects 2368832SAli.Saidi@ARM.com * that intend to issues requests into the memory system must request an id 2378832SAli.Saidi@ARM.com * in the init() phase of startup. All master ids must be fixed by the 2388832SAli.Saidi@ARM.com * regStats() phase that immediately preceeds it. This allows objects in the 2398832SAli.Saidi@ARM.com * memory system to understand how many masters may exist and 2408832SAli.Saidi@ARM.com * appropriately name the bins of their per-master stats before the stats 2418832SAli.Saidi@ARM.com * are finalized 2428832SAli.Saidi@ARM.com */ 2438832SAli.Saidi@ARM.com MasterID getMasterId(std::string req_name); 2448832SAli.Saidi@ARM.com 2458832SAli.Saidi@ARM.com /** Get the name of an object for a given request id. 2468832SAli.Saidi@ARM.com */ 2478832SAli.Saidi@ARM.com std::string getMasterName(MasterID master_id); 2488832SAli.Saidi@ARM.com 2498832SAli.Saidi@ARM.com /** Get the number of masters registered in the system */ 2508832SAli.Saidi@ARM.com MasterID maxMasters() 2518832SAli.Saidi@ARM.com { 2528832SAli.Saidi@ARM.com return masterIds.size(); 2538832SAli.Saidi@ARM.com } 2548832SAli.Saidi@ARM.com 2558666SPrakash.Ramrakhyani@arm.com virtual void regStats(); 2567914SBrad.Beckmann@amd.com /** 2577914SBrad.Beckmann@amd.com * Called by pseudo_inst to track the number of work items started by this 2587914SBrad.Beckmann@amd.com * system. 2597914SBrad.Beckmann@amd.com */ 2608666SPrakash.Ramrakhyani@arm.com uint64_t 2617914SBrad.Beckmann@amd.com incWorkItemsBegin() 2627914SBrad.Beckmann@amd.com { 2637914SBrad.Beckmann@amd.com return ++workItemsBegin; 2647914SBrad.Beckmann@amd.com } 2657914SBrad.Beckmann@amd.com 2667914SBrad.Beckmann@amd.com /** 2677914SBrad.Beckmann@amd.com * Called by pseudo_inst to track the number of work items completed by 2687914SBrad.Beckmann@amd.com * this system. 2697914SBrad.Beckmann@amd.com */ 2707914SBrad.Beckmann@amd.com uint64_t 2717914SBrad.Beckmann@amd.com incWorkItemsEnd() 2727914SBrad.Beckmann@amd.com { 2737914SBrad.Beckmann@amd.com return ++workItemsEnd; 2747914SBrad.Beckmann@amd.com } 2757914SBrad.Beckmann@amd.com 2767914SBrad.Beckmann@amd.com /** 2777914SBrad.Beckmann@amd.com * Called by pseudo_inst to mark the cpus actively executing work items. 2787914SBrad.Beckmann@amd.com * Returns the total number of cpus that have executed work item begin or 2797914SBrad.Beckmann@amd.com * ends. 2807914SBrad.Beckmann@amd.com */ 2817914SBrad.Beckmann@amd.com int 2827914SBrad.Beckmann@amd.com markWorkItem(int index) 2837914SBrad.Beckmann@amd.com { 2847914SBrad.Beckmann@amd.com int count = 0; 2857914SBrad.Beckmann@amd.com assert(index < activeCpus.size()); 2867914SBrad.Beckmann@amd.com activeCpus[index] = true; 2877914SBrad.Beckmann@amd.com for (std::vector<bool>::iterator i = activeCpus.begin(); 2887914SBrad.Beckmann@amd.com i < activeCpus.end(); i++) { 2897914SBrad.Beckmann@amd.com if (*i) count++; 2907914SBrad.Beckmann@amd.com } 2917914SBrad.Beckmann@amd.com return count; 2927914SBrad.Beckmann@amd.com } 2932901Ssaidi@eecs.umich.edu 2948666SPrakash.Ramrakhyani@arm.com inline void workItemBegin(uint32_t tid, uint32_t workid) 2958666SPrakash.Ramrakhyani@arm.com { 2968666SPrakash.Ramrakhyani@arm.com std::pair<uint32_t,uint32_t> p(tid, workid); 2978666SPrakash.Ramrakhyani@arm.com lastWorkItemStarted[p] = curTick(); 2988666SPrakash.Ramrakhyani@arm.com } 2998666SPrakash.Ramrakhyani@arm.com 3008666SPrakash.Ramrakhyani@arm.com void workItemEnd(uint32_t tid, uint32_t workid); 3018666SPrakash.Ramrakhyani@arm.com 3021885SN/A /** 3031885SN/A * Fix up an address used to match PCs for hooking simulator 3041885SN/A * events on to target function executions. See comment in 3051885SN/A * system.cc for details. 3061885SN/A */ 3078769Sgblack@eecs.umich.edu virtual Addr fixFuncEventAddr(Addr addr) 3088769Sgblack@eecs.umich.edu { 3098769Sgblack@eecs.umich.edu panic("Base fixFuncEventAddr not implemented.\n"); 3108769Sgblack@eecs.umich.edu } 3111885SN/A 3121885SN/A /** 3131885SN/A * Add a function-based event to the given function, to be looked 3141885SN/A * up in the specified symbol table. 3151885SN/A */ 3161885SN/A template <class T> 3172989Ssaidi@eecs.umich.edu T *addFuncEvent(SymbolTable *symtab, const char *lbl) 3181885SN/A { 3191913SN/A Addr addr = 0; // initialize only to avoid compiler warning 3201885SN/A 3211885SN/A if (symtab->findAddress(lbl, addr)) { 3221885SN/A T *ev = new T(&pcEventQueue, lbl, fixFuncEventAddr(addr)); 3231885SN/A return ev; 3241885SN/A } 3251885SN/A 3261885SN/A return NULL; 3271885SN/A } 3281885SN/A 3291885SN/A /** Add a function-based event to kernel code. */ 3301885SN/A template <class T> 3312989Ssaidi@eecs.umich.edu T *addKernelFuncEvent(const char *lbl) 3321885SN/A { 3331885SN/A return addFuncEvent<T>(kernelSymtab, lbl); 3341885SN/A } 3351885SN/A 33677SN/A public: 3376658Snate@binkert.org std::vector<BaseRemoteGDB *> remoteGDB; 3381070SN/A std::vector<GDBListener *> gdbListen; 3393960Sgblack@eecs.umich.edu bool breakpoint(); 3401070SN/A 3411070SN/A public: 3424762Snate@binkert.org typedef SystemParams Params; 3431070SN/A 3442158SN/A protected: 3452158SN/A Params *_params; 3461070SN/A 3472158SN/A public: 3481070SN/A System(Params *p); 3492SN/A ~System(); 3502SN/A 3517733SAli.Saidi@ARM.com void initState(); 3521129SN/A 3532158SN/A const Params *params() const { return (const Params *)_params; } 3542158SN/A 3551070SN/A public: 3562378SN/A 3571070SN/A /** 3581070SN/A * Returns the addess the kernel starts at. 3591070SN/A * @return address the kernel starts at 3601070SN/A */ 3611070SN/A Addr getKernelStart() const { return kernelStart; } 3621070SN/A 3631070SN/A /** 3641070SN/A * Returns the addess the kernel ends at. 3651070SN/A * @return address the kernel ends at 3661070SN/A */ 3671070SN/A Addr getKernelEnd() const { return kernelEnd; } 3681070SN/A 3691070SN/A /** 3701070SN/A * Returns the addess the entry point to the kernel code. 3711070SN/A * @return entry point of the kernel code 3721070SN/A */ 3731070SN/A Addr getKernelEntry() const { return kernelEntry; } 3741070SN/A 3758601Ssteve.reinhardt@amd.com /// Allocate npages contiguous unused physical pages 3768601Ssteve.reinhardt@amd.com /// @return Starting address of first page 3778601Ssteve.reinhardt@amd.com Addr allocPhysPages(int npages); 3782378SN/A 3795718Shsul@eecs.umich.edu int registerThreadContext(ThreadContext *tc, int assigned=-1); 3805713Shsul@eecs.umich.edu void replaceThreadContext(ThreadContext *tc, int context_id); 3811070SN/A 3821070SN/A void serialize(std::ostream &os); 3831070SN/A void unserialize(Checkpoint *cp, const std::string §ion); 3847897Shestness@cs.utexas.edu virtual void resume(); 3852SN/A 38677SN/A public: 3877897Shestness@cs.utexas.edu Counter totalNumInsts; 3887897Shestness@cs.utexas.edu EventQueue instEventQueue; 3898666SPrakash.Ramrakhyani@arm.com std::map<std::pair<uint32_t,uint32_t>, Tick> lastWorkItemStarted; 3908666SPrakash.Ramrakhyani@arm.com std::map<uint32_t, Stats::Histogram*> workItemStats; 3917897Shestness@cs.utexas.edu 3922SN/A //////////////////////////////////////////// 3932SN/A // 3942SN/A // STATIC GLOBAL SYSTEM LIST 3952SN/A // 3962SN/A //////////////////////////////////////////// 3972SN/A 3982SN/A static std::vector<System *> systemList; 3992SN/A static int numSystemsRunning; 4002SN/A 4012SN/A static void printSystems(); 4022158SN/A 4039112Smarc.orr@gmail.com // For futex system call 4049112Smarc.orr@gmail.com std::map<uint64_t, std::list<ThreadContext *> * > futexMap; 4059112Smarc.orr@gmail.com 4062158SN/A 4072SN/A}; 4082SN/A 4092SN/A#endif // __SYSTEM_HH__ 410