system.hh revision 8703
12SN/A/* 28703Sandreas.hansson@arm.com * Copyright (c) 2012 ARM Limited 38703Sandreas.hansson@arm.com * All rights reserved 48703Sandreas.hansson@arm.com * 58703Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68703Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78703Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88703Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98703Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108703Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118703Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128703Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138703Sandreas.hansson@arm.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422665Ssaidi@eecs.umich.edu * Lisa Hsu 432665Ssaidi@eecs.umich.edu * Nathan Binkert 447897Shestness@cs.utexas.edu * Rick Strong 452SN/A */ 462SN/A 472SN/A#ifndef __SYSTEM_HH__ 482SN/A#define __SYSTEM_HH__ 492SN/A 502SN/A#include <string> 5175SN/A#include <vector> 522SN/A 532439SN/A#include "base/loader/symtab.hh" 542439SN/A#include "base/misc.hh" 55603SN/A#include "base/statistics.hh" 562986Sgblack@eecs.umich.edu#include "config/full_system.hh" 57603SN/A#include "cpu/pc_event.hh" 584762Snate@binkert.org#include "enums/MemoryMode.hh" 598703Sandreas.hansson@arm.com#include "mem/mem_object.hh" 602520SN/A#include "mem/port.hh" 614762Snate@binkert.org#include "params/System.hh" 626658Snate@binkert.org 632378SN/A#if FULL_SYSTEM 64722SN/A#include "kern/system_events.hh" 652378SN/A#endif 66312SN/A 671634SN/Aclass BaseCPU; 682680Sktlim@umich.educlass ThreadContext; 691634SN/Aclass ObjectFile; 702521SN/Aclass PhysicalMemory; 712378SN/A 722378SN/A#if FULL_SYSTEM 73803SN/Aclass Platform; 747723SAli.Saidi@ARM.comclass FunctionalPort; 757723SAli.Saidi@ARM.comclass VirtualPort; 763960Sgblack@eecs.umich.edu#endif 772378SN/Aclass GDBListener; 786658Snate@binkert.orgclass BaseRemoteGDB; 792SN/A 808703Sandreas.hansson@arm.comclass System : public MemObject 812SN/A{ 828703Sandreas.hansson@arm.com private: 838703Sandreas.hansson@arm.com 848703Sandreas.hansson@arm.com /** 858703Sandreas.hansson@arm.com * Private class for the system port which is only used as a 868703Sandreas.hansson@arm.com * master for debug access and for non-structural entities that do 878703Sandreas.hansson@arm.com * not have a port of their own. 888703Sandreas.hansson@arm.com */ 898703Sandreas.hansson@arm.com class SystemPort : public Port 908703Sandreas.hansson@arm.com { 918703Sandreas.hansson@arm.com public: 928703Sandreas.hansson@arm.com 938703Sandreas.hansson@arm.com /** 948703Sandreas.hansson@arm.com * Create a system port with a name and an owner. 958703Sandreas.hansson@arm.com */ 968703Sandreas.hansson@arm.com SystemPort(const std::string &_name, MemObject *_owner) 978703Sandreas.hansson@arm.com : Port(_name, _owner) 988703Sandreas.hansson@arm.com { } 998703Sandreas.hansson@arm.com bool recvTiming(PacketPtr pkt) 1008703Sandreas.hansson@arm.com { panic("SystemPort does not receive timing!\n"); return false; } 1018703Sandreas.hansson@arm.com Tick recvAtomic(PacketPtr pkt) 1028703Sandreas.hansson@arm.com { panic("SystemPort does not receive atomic!\n"); return 0; } 1038703Sandreas.hansson@arm.com void recvFunctional(PacketPtr pkt) 1048703Sandreas.hansson@arm.com { panic("SystemPort does not receive functional!\n"); } 1058703Sandreas.hansson@arm.com void recvStatusChange(Status status) { } 1068703Sandreas.hansson@arm.com 1078703Sandreas.hansson@arm.com }; 1088703Sandreas.hansson@arm.com 1098703Sandreas.hansson@arm.com SystemPort _systemPort; 1108703Sandreas.hansson@arm.com 111603SN/A public: 1122901Ssaidi@eecs.umich.edu 1138703Sandreas.hansson@arm.com /** 1148703Sandreas.hansson@arm.com * Get a pointer to the system port that can be used by 1158703Sandreas.hansson@arm.com * non-structural simulation objects like processes or threads, or 1168703Sandreas.hansson@arm.com * external entities like loaders and debuggers, etc, to access 1178703Sandreas.hansson@arm.com * the memory system. 1188703Sandreas.hansson@arm.com * 1198703Sandreas.hansson@arm.com * @return a pointer to the system port we own 1208703Sandreas.hansson@arm.com */ 1218703Sandreas.hansson@arm.com Port* getSystemPort() { return &_systemPort; } 1228703Sandreas.hansson@arm.com 1238703Sandreas.hansson@arm.com /** 1248703Sandreas.hansson@arm.com * Additional function to return the Port of a memory object. 1258703Sandreas.hansson@arm.com */ 1268703Sandreas.hansson@arm.com Port *getPort(const std::string &if_name, int idx = -1); 1278703Sandreas.hansson@arm.com 1282902Ssaidi@eecs.umich.edu static const char *MemoryModeStrings[3]; 1292902Ssaidi@eecs.umich.edu 1304762Snate@binkert.org Enums::MemoryMode 1314762Snate@binkert.org getMemoryMode() 1324762Snate@binkert.org { 1334762Snate@binkert.org assert(memoryMode); 1344762Snate@binkert.org return memoryMode; 1354762Snate@binkert.org } 1362901Ssaidi@eecs.umich.edu 1372901Ssaidi@eecs.umich.edu /** Change the memory mode of the system. This should only be called by the 1382901Ssaidi@eecs.umich.edu * python!! 1392901Ssaidi@eecs.umich.edu * @param mode Mode to change to (atomic/timing) 1402901Ssaidi@eecs.umich.edu */ 1414762Snate@binkert.org void setMemoryMode(Enums::MemoryMode mode); 1422901Ssaidi@eecs.umich.edu 1432521SN/A PhysicalMemory *physmem; 1442SN/A PCEventQueue pcEventQueue; 1452SN/A 1462680Sktlim@umich.edu std::vector<ThreadContext *> threadContexts; 1475714Shsul@eecs.umich.edu int _numContexts; 1481806SN/A 1496221Snate@binkert.org ThreadContext *getThreadContext(ThreadID tid) 1505713Shsul@eecs.umich.edu { 1515713Shsul@eecs.umich.edu return threadContexts[tid]; 1525713Shsul@eecs.umich.edu } 1535713Shsul@eecs.umich.edu 1545714Shsul@eecs.umich.edu int numContexts() 1551806SN/A { 1566227Snate@binkert.org assert(_numContexts == (int)threadContexts.size()); 1575714Shsul@eecs.umich.edu return _numContexts; 1581806SN/A } 159180SN/A 1606029Ssteve.reinhardt@amd.com /** Return number of running (non-halted) thread contexts in 1616029Ssteve.reinhardt@amd.com * system. These threads could be Active or Suspended. */ 1626029Ssteve.reinhardt@amd.com int numRunningContexts(); 1636029Ssteve.reinhardt@amd.com 1648460SAli.Saidi@ARM.com /** List to store ranges of memories in this system */ 1658460SAli.Saidi@ARM.com AddrRangeList memRanges; 1668460SAli.Saidi@ARM.com 1678460SAli.Saidi@ARM.com /** check if an address points to valid system memory 1688460SAli.Saidi@ARM.com * and thus we can fetch instructions out of it 1698460SAli.Saidi@ARM.com */ 1708460SAli.Saidi@ARM.com bool isMemory(const Addr addr) const; 1718460SAli.Saidi@ARM.com 1722378SN/A#if FULL_SYSTEM 1732378SN/A Platform *platform; 1742378SN/A uint64_t init_param; 1752378SN/A 1762520SN/A /** Port to physical memory used for writing object files into ram at 1772520SN/A * boot.*/ 1787723SAli.Saidi@ARM.com FunctionalPort *functionalPort; 1797723SAli.Saidi@ARM.com VirtualPort *virtPort; 1802520SN/A 1811885SN/A /** kernel symbol table */ 1821070SN/A SymbolTable *kernelSymtab; 183954SN/A 1841070SN/A /** Object pointer for the kernel code */ 1851070SN/A ObjectFile *kernel; 1861070SN/A 1871070SN/A /** Begining of kernel code */ 1881070SN/A Addr kernelStart; 1891070SN/A 1901070SN/A /** End of kernel code */ 1911070SN/A Addr kernelEnd; 1921070SN/A 1931070SN/A /** Entry point in the kernel to start at */ 1941070SN/A Addr kernelEntry; 1951070SN/A 1967580SAli.Saidi@arm.com /** Mask that should be anded for binary/symbol loading. 1977580SAli.Saidi@arm.com * This allows one two different OS requirements for the same ISA to be 1987580SAli.Saidi@arm.com * handled. Some OSes are compiled for a virtual address and need to be 1997580SAli.Saidi@arm.com * loaded into physical memory that starts at address 0, while other 2007580SAli.Saidi@arm.com * bare metal tools generate images that start at address 0. 2017580SAli.Saidi@arm.com */ 2027580SAli.Saidi@arm.com Addr loadAddrMask; 2037580SAli.Saidi@arm.com 2042378SN/A#else 2052378SN/A 2067770SAli.Saidi@ARM.com Addr pagePtr; 2072378SN/A 2084997Sgblack@eecs.umich.edu protected: 2097770SAli.Saidi@ARM.com uint64_t nextPID; 2104997Sgblack@eecs.umich.edu 2114997Sgblack@eecs.umich.edu public: 2124997Sgblack@eecs.umich.edu uint64_t allocatePID() 2134997Sgblack@eecs.umich.edu { 2147770SAli.Saidi@ARM.com return nextPID++; 2154997Sgblack@eecs.umich.edu } 2164997Sgblack@eecs.umich.edu 2175795Ssaidi@eecs.umich.edu /** Amount of physical memory that is still free */ 2185795Ssaidi@eecs.umich.edu Addr freeMemSize(); 2195795Ssaidi@eecs.umich.edu 2205795Ssaidi@eecs.umich.edu /** Amount of physical memory that exists */ 2215795Ssaidi@eecs.umich.edu Addr memSize(); 2225795Ssaidi@eecs.umich.edu 2232378SN/A 2242378SN/A#endif // FULL_SYSTEM 2252378SN/A 2261885SN/A protected: 2274762Snate@binkert.org Enums::MemoryMode memoryMode; 2287914SBrad.Beckmann@amd.com uint64_t workItemsBegin; 2297914SBrad.Beckmann@amd.com uint64_t workItemsEnd; 2308666SPrakash.Ramrakhyani@arm.com uint32_t numWorkIds; 2317914SBrad.Beckmann@amd.com std::vector<bool> activeCpus; 2327914SBrad.Beckmann@amd.com 2337914SBrad.Beckmann@amd.com public: 2348666SPrakash.Ramrakhyani@arm.com virtual void regStats(); 2357914SBrad.Beckmann@amd.com /** 2367914SBrad.Beckmann@amd.com * Called by pseudo_inst to track the number of work items started by this 2377914SBrad.Beckmann@amd.com * system. 2387914SBrad.Beckmann@amd.com */ 2398666SPrakash.Ramrakhyani@arm.com uint64_t 2407914SBrad.Beckmann@amd.com incWorkItemsBegin() 2417914SBrad.Beckmann@amd.com { 2427914SBrad.Beckmann@amd.com return ++workItemsBegin; 2437914SBrad.Beckmann@amd.com } 2447914SBrad.Beckmann@amd.com 2457914SBrad.Beckmann@amd.com /** 2467914SBrad.Beckmann@amd.com * Called by pseudo_inst to track the number of work items completed by 2477914SBrad.Beckmann@amd.com * this system. 2487914SBrad.Beckmann@amd.com */ 2497914SBrad.Beckmann@amd.com uint64_t 2507914SBrad.Beckmann@amd.com incWorkItemsEnd() 2517914SBrad.Beckmann@amd.com { 2527914SBrad.Beckmann@amd.com return ++workItemsEnd; 2537914SBrad.Beckmann@amd.com } 2547914SBrad.Beckmann@amd.com 2557914SBrad.Beckmann@amd.com /** 2567914SBrad.Beckmann@amd.com * Called by pseudo_inst to mark the cpus actively executing work items. 2577914SBrad.Beckmann@amd.com * Returns the total number of cpus that have executed work item begin or 2587914SBrad.Beckmann@amd.com * ends. 2597914SBrad.Beckmann@amd.com */ 2607914SBrad.Beckmann@amd.com int 2617914SBrad.Beckmann@amd.com markWorkItem(int index) 2627914SBrad.Beckmann@amd.com { 2637914SBrad.Beckmann@amd.com int count = 0; 2647914SBrad.Beckmann@amd.com assert(index < activeCpus.size()); 2657914SBrad.Beckmann@amd.com activeCpus[index] = true; 2667914SBrad.Beckmann@amd.com for (std::vector<bool>::iterator i = activeCpus.begin(); 2677914SBrad.Beckmann@amd.com i < activeCpus.end(); i++) { 2687914SBrad.Beckmann@amd.com if (*i) count++; 2697914SBrad.Beckmann@amd.com } 2707914SBrad.Beckmann@amd.com return count; 2717914SBrad.Beckmann@amd.com } 2722901Ssaidi@eecs.umich.edu 2738666SPrakash.Ramrakhyani@arm.com inline void workItemBegin(uint32_t tid, uint32_t workid) 2748666SPrakash.Ramrakhyani@arm.com { 2758666SPrakash.Ramrakhyani@arm.com std::pair<uint32_t,uint32_t> p(tid, workid); 2768666SPrakash.Ramrakhyani@arm.com lastWorkItemStarted[p] = curTick(); 2778666SPrakash.Ramrakhyani@arm.com } 2788666SPrakash.Ramrakhyani@arm.com 2798666SPrakash.Ramrakhyani@arm.com void workItemEnd(uint32_t tid, uint32_t workid); 2808666SPrakash.Ramrakhyani@arm.com 2812424SN/A#if FULL_SYSTEM 2821885SN/A /** 2831885SN/A * Fix up an address used to match PCs for hooking simulator 2841885SN/A * events on to target function executions. See comment in 2851885SN/A * system.cc for details. 2861885SN/A */ 2872158SN/A virtual Addr fixFuncEventAddr(Addr addr) = 0; 2881885SN/A 2891885SN/A /** 2901885SN/A * Add a function-based event to the given function, to be looked 2911885SN/A * up in the specified symbol table. 2921885SN/A */ 2931885SN/A template <class T> 2942989Ssaidi@eecs.umich.edu T *addFuncEvent(SymbolTable *symtab, const char *lbl) 2951885SN/A { 2961913SN/A Addr addr = 0; // initialize only to avoid compiler warning 2971885SN/A 2981885SN/A if (symtab->findAddress(lbl, addr)) { 2991885SN/A T *ev = new T(&pcEventQueue, lbl, fixFuncEventAddr(addr)); 3001885SN/A return ev; 3011885SN/A } 3021885SN/A 3031885SN/A return NULL; 3041885SN/A } 3051885SN/A 3061885SN/A /** Add a function-based event to kernel code. */ 3071885SN/A template <class T> 3082989Ssaidi@eecs.umich.edu T *addKernelFuncEvent(const char *lbl) 3091885SN/A { 3101885SN/A return addFuncEvent<T>(kernelSymtab, lbl); 3111885SN/A } 3121885SN/A 3132378SN/A#endif 31477SN/A public: 3156658Snate@binkert.org std::vector<BaseRemoteGDB *> remoteGDB; 3161070SN/A std::vector<GDBListener *> gdbListen; 3173960Sgblack@eecs.umich.edu bool breakpoint(); 3181070SN/A 3191070SN/A public: 3204762Snate@binkert.org typedef SystemParams Params; 3211070SN/A 3222158SN/A protected: 3232158SN/A Params *_params; 3241070SN/A 3252158SN/A public: 3261070SN/A System(Params *p); 3272SN/A ~System(); 3282SN/A 3297733SAli.Saidi@ARM.com void initState(); 3301129SN/A 3312158SN/A const Params *params() const { return (const Params *)_params; } 3322158SN/A 3331070SN/A public: 3342378SN/A 3352378SN/A#if FULL_SYSTEM 3361070SN/A /** 3371070SN/A * Returns the addess the kernel starts at. 3381070SN/A * @return address the kernel starts at 3391070SN/A */ 3401070SN/A Addr getKernelStart() const { return kernelStart; } 3411070SN/A 3421070SN/A /** 3431070SN/A * Returns the addess the kernel ends at. 3441070SN/A * @return address the kernel ends at 3451070SN/A */ 3461070SN/A Addr getKernelEnd() const { return kernelEnd; } 3471070SN/A 3481070SN/A /** 3491070SN/A * Returns the addess the entry point to the kernel code. 3501070SN/A * @return entry point of the kernel code 3511070SN/A */ 3521070SN/A Addr getKernelEntry() const { return kernelEntry; } 3531070SN/A 3542378SN/A#else 3552378SN/A 3568601Ssteve.reinhardt@amd.com /// Allocate npages contiguous unused physical pages 3578601Ssteve.reinhardt@amd.com /// @return Starting address of first page 3588601Ssteve.reinhardt@amd.com Addr allocPhysPages(int npages); 3592378SN/A 3602378SN/A#endif // FULL_SYSTEM 3612378SN/A 3625718Shsul@eecs.umich.edu int registerThreadContext(ThreadContext *tc, int assigned=-1); 3635713Shsul@eecs.umich.edu void replaceThreadContext(ThreadContext *tc, int context_id); 3641070SN/A 3651070SN/A void serialize(std::ostream &os); 3661070SN/A void unserialize(Checkpoint *cp, const std::string §ion); 3677897Shestness@cs.utexas.edu virtual void resume(); 3682SN/A 36977SN/A public: 3707897Shestness@cs.utexas.edu Counter totalNumInsts; 3717897Shestness@cs.utexas.edu EventQueue instEventQueue; 3728666SPrakash.Ramrakhyani@arm.com std::map<std::pair<uint32_t,uint32_t>, Tick> lastWorkItemStarted; 3738666SPrakash.Ramrakhyani@arm.com std::map<uint32_t, Stats::Histogram*> workItemStats; 3747897Shestness@cs.utexas.edu 3752SN/A //////////////////////////////////////////// 3762SN/A // 3772SN/A // STATIC GLOBAL SYSTEM LIST 3782SN/A // 3792SN/A //////////////////////////////////////////// 3802SN/A 3812SN/A static std::vector<System *> systemList; 3822SN/A static int numSystemsRunning; 3832SN/A 3842SN/A static void printSystems(); 3852158SN/A 3862158SN/A 3872SN/A}; 3882SN/A 3892SN/A#endif // __SYSTEM_HH__ 390