system.hh revision 12515
12SN/A/* 210466Sandreas.hansson@arm.com * Copyright (c) 2012, 2014 ARM Limited 38703Sandreas.hansson@arm.com * All rights reserved 48703Sandreas.hansson@arm.com * 58703Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68703Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78703Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88703Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98703Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108703Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118703Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128703Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138703Sandreas.hansson@arm.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422665Ssaidi@eecs.umich.edu * Lisa Hsu 432665Ssaidi@eecs.umich.edu * Nathan Binkert 447897Shestness@cs.utexas.edu * Rick Strong 452SN/A */ 462SN/A 472SN/A#ifndef __SYSTEM_HH__ 482SN/A#define __SYSTEM_HH__ 492SN/A 502SN/A#include <string> 5111911SBrandon.Potter@amd.com#include <unordered_map> 529645SAndreas.Sandberg@ARM.com#include <utility> 5375SN/A#include <vector> 542SN/A 5510466Sandreas.hansson@arm.com#include "arch/isa_traits.hh" 562439SN/A#include "base/loader/symtab.hh" 57603SN/A#include "base/statistics.hh" 5810466Sandreas.hansson@arm.com#include "config/the_isa.hh" 594762Snate@binkert.org#include "enums/MemoryMode.hh" 608703Sandreas.hansson@arm.com#include "mem/mem_object.hh" 6111911SBrandon.Potter@amd.com#include "mem/physical.hh" 622520SN/A#include "mem/port.hh" 639847Sandreas.hansson@arm.com#include "mem/port_proxy.hh" 644762Snate@binkert.org#include "params/System.hh" 6511911SBrandon.Potter@amd.com#include "sim/futex_map.hh" 6611909SBrandon.Potter@amd.com#include "sim/se_signal.hh" 676658Snate@binkert.org 6810494Sandreas.hansson@arm.com/** 6910494Sandreas.hansson@arm.com * To avoid linking errors with LTO, only include the header if we 7010494Sandreas.hansson@arm.com * actually have the definition. 7110494Sandreas.hansson@arm.com */ 7210494Sandreas.hansson@arm.com#if THE_ISA != NULL_ISA 7310494Sandreas.hansson@arm.com#include "cpu/pc_event.hh" 7411911SBrandon.Potter@amd.com 7510494Sandreas.hansson@arm.com#endif 7610494Sandreas.hansson@arm.com 778769Sgblack@eecs.umich.educlass BaseRemoteGDB; 7811839SCurtis.Dunham@arm.comclass KvmVM; 791634SN/Aclass ObjectFile; 808769Sgblack@eecs.umich.educlass ThreadContext; 812SN/A 828703Sandreas.hansson@arm.comclass System : public MemObject 832SN/A{ 848703Sandreas.hansson@arm.com private: 858703Sandreas.hansson@arm.com 868703Sandreas.hansson@arm.com /** 878703Sandreas.hansson@arm.com * Private class for the system port which is only used as a 888703Sandreas.hansson@arm.com * master for debug access and for non-structural entities that do 898703Sandreas.hansson@arm.com * not have a port of their own. 908703Sandreas.hansson@arm.com */ 918922Swilliam.wang@arm.com class SystemPort : public MasterPort 928703Sandreas.hansson@arm.com { 938703Sandreas.hansson@arm.com public: 948703Sandreas.hansson@arm.com 958703Sandreas.hansson@arm.com /** 968703Sandreas.hansson@arm.com * Create a system port with a name and an owner. 978703Sandreas.hansson@arm.com */ 988703Sandreas.hansson@arm.com SystemPort(const std::string &_name, MemObject *_owner) 998922Swilliam.wang@arm.com : MasterPort(_name, _owner) 1008703Sandreas.hansson@arm.com { } 10111169Sandreas.hansson@arm.com bool recvTimingResp(PacketPtr pkt) override 1028703Sandreas.hansson@arm.com { panic("SystemPort does not receive timing!\n"); return false; } 10311169Sandreas.hansson@arm.com void recvReqRetry() override 1048922Swilliam.wang@arm.com { panic("SystemPort does not expect retry!\n"); } 1058703Sandreas.hansson@arm.com }; 1068703Sandreas.hansson@arm.com 1078703Sandreas.hansson@arm.com SystemPort _systemPort; 1088703Sandreas.hansson@arm.com 109603SN/A public: 1102901Ssaidi@eecs.umich.edu 1118703Sandreas.hansson@arm.com /** 1128706Sandreas.hansson@arm.com * After all objects have been created and all ports are 1138706Sandreas.hansson@arm.com * connected, check that the system port is connected. 1148706Sandreas.hansson@arm.com */ 11511169Sandreas.hansson@arm.com void init() override; 1168706Sandreas.hansson@arm.com 1178706Sandreas.hansson@arm.com /** 1188852Sandreas.hansson@arm.com * Get a reference to the system port that can be used by 1198703Sandreas.hansson@arm.com * non-structural simulation objects like processes or threads, or 1208703Sandreas.hansson@arm.com * external entities like loaders and debuggers, etc, to access 1218703Sandreas.hansson@arm.com * the memory system. 1228703Sandreas.hansson@arm.com * 1238852Sandreas.hansson@arm.com * @return a reference to the system port we own 1248703Sandreas.hansson@arm.com */ 1258922Swilliam.wang@arm.com MasterPort& getSystemPort() { return _systemPort; } 1268703Sandreas.hansson@arm.com 1278703Sandreas.hansson@arm.com /** 1288703Sandreas.hansson@arm.com * Additional function to return the Port of a memory object. 1298703Sandreas.hansson@arm.com */ 1309294Sandreas.hansson@arm.com BaseMasterPort& getMasterPort(const std::string &if_name, 13111169Sandreas.hansson@arm.com PortID idx = InvalidPortID) override; 1328703Sandreas.hansson@arm.com 1339524SAndreas.Sandberg@ARM.com /** @{ */ 1349524SAndreas.Sandberg@ARM.com /** 1359524SAndreas.Sandberg@ARM.com * Is the system in atomic mode? 1369524SAndreas.Sandberg@ARM.com * 1379524SAndreas.Sandberg@ARM.com * There are currently two different atomic memory modes: 1389524SAndreas.Sandberg@ARM.com * 'atomic', which supports caches; and 'atomic_noncaching', which 1399524SAndreas.Sandberg@ARM.com * bypasses caches. The latter is used by hardware virtualized 1409524SAndreas.Sandberg@ARM.com * CPUs. SimObjects are expected to use Port::sendAtomic() and 1419524SAndreas.Sandberg@ARM.com * Port::recvAtomic() when accessing memory in this mode. 1429524SAndreas.Sandberg@ARM.com */ 1439524SAndreas.Sandberg@ARM.com bool isAtomicMode() const { 1449524SAndreas.Sandberg@ARM.com return memoryMode == Enums::atomic || 1459524SAndreas.Sandberg@ARM.com memoryMode == Enums::atomic_noncaching; 1464762Snate@binkert.org } 1472901Ssaidi@eecs.umich.edu 1489524SAndreas.Sandberg@ARM.com /** 1499524SAndreas.Sandberg@ARM.com * Is the system in timing mode? 1509524SAndreas.Sandberg@ARM.com * 1519524SAndreas.Sandberg@ARM.com * SimObjects are expected to use Port::sendTiming() and 1529524SAndreas.Sandberg@ARM.com * Port::recvTiming() when accessing memory in this mode. 1539524SAndreas.Sandberg@ARM.com */ 1549524SAndreas.Sandberg@ARM.com bool isTimingMode() const { 1559524SAndreas.Sandberg@ARM.com return memoryMode == Enums::timing; 1569524SAndreas.Sandberg@ARM.com } 1579524SAndreas.Sandberg@ARM.com 1589524SAndreas.Sandberg@ARM.com /** 1599524SAndreas.Sandberg@ARM.com * Should caches be bypassed? 1609524SAndreas.Sandberg@ARM.com * 1619524SAndreas.Sandberg@ARM.com * Some CPUs need to bypass caches to allow direct memory 1629524SAndreas.Sandberg@ARM.com * accesses, which is required for hardware virtualization. 1639524SAndreas.Sandberg@ARM.com */ 1649524SAndreas.Sandberg@ARM.com bool bypassCaches() const { 1659524SAndreas.Sandberg@ARM.com return memoryMode == Enums::atomic_noncaching; 1669524SAndreas.Sandberg@ARM.com } 1679524SAndreas.Sandberg@ARM.com /** @} */ 1689524SAndreas.Sandberg@ARM.com 1699524SAndreas.Sandberg@ARM.com /** @{ */ 1709524SAndreas.Sandberg@ARM.com /** 1719524SAndreas.Sandberg@ARM.com * Get the memory mode of the system. 1729524SAndreas.Sandberg@ARM.com * 1739524SAndreas.Sandberg@ARM.com * \warn This should only be used by the Python world. The C++ 1749524SAndreas.Sandberg@ARM.com * world should use one of the query functions above 1759524SAndreas.Sandberg@ARM.com * (isAtomicMode(), isTimingMode(), bypassCaches()). 1769524SAndreas.Sandberg@ARM.com */ 1779524SAndreas.Sandberg@ARM.com Enums::MemoryMode getMemoryMode() const { return memoryMode; } 1789524SAndreas.Sandberg@ARM.com 1799524SAndreas.Sandberg@ARM.com /** 1809524SAndreas.Sandberg@ARM.com * Change the memory mode of the system. 1819524SAndreas.Sandberg@ARM.com * 1829524SAndreas.Sandberg@ARM.com * \warn This should only be called by the Python! 1839524SAndreas.Sandberg@ARM.com * 1849524SAndreas.Sandberg@ARM.com * @param mode Mode to change to (atomic/timing/...) 1852901Ssaidi@eecs.umich.edu */ 1864762Snate@binkert.org void setMemoryMode(Enums::MemoryMode mode); 1879524SAndreas.Sandberg@ARM.com /** @} */ 1882901Ssaidi@eecs.umich.edu 1899814Sandreas.hansson@arm.com /** 1909814Sandreas.hansson@arm.com * Get the cache line size of the system. 1919814Sandreas.hansson@arm.com */ 1929814Sandreas.hansson@arm.com unsigned int cacheLineSize() const { return _cacheLineSize; } 1939814Sandreas.hansson@arm.com 1949850Sandreas.hansson@arm.com#if THE_ISA != NULL_ISA 1952SN/A PCEventQueue pcEventQueue; 1969850Sandreas.hansson@arm.com#endif 1972SN/A 1982680Sktlim@umich.edu std::vector<ThreadContext *> threadContexts; 19911146Smitch.hayenga@arm.com const bool multiThread; 2001806SN/A 20111005Sandreas.sandberg@arm.com ThreadContext *getThreadContext(ContextID tid) 2025713Shsul@eecs.umich.edu { 2035713Shsul@eecs.umich.edu return threadContexts[tid]; 2045713Shsul@eecs.umich.edu } 2055713Shsul@eecs.umich.edu 20612515Sgiacomo.travaglini@arm.com unsigned numContexts() const { return threadContexts.size(); } 207180SN/A 2086029Ssteve.reinhardt@amd.com /** Return number of running (non-halted) thread contexts in 2096029Ssteve.reinhardt@amd.com * system. These threads could be Active or Suspended. */ 2106029Ssteve.reinhardt@amd.com int numRunningContexts(); 2116029Ssteve.reinhardt@amd.com 2128765Sgblack@eecs.umich.edu Addr pagePtr; 2138765Sgblack@eecs.umich.edu 2142378SN/A uint64_t init_param; 2152378SN/A 2162520SN/A /** Port to physical memory used for writing object files into ram at 2172520SN/A * boot.*/ 2188852Sandreas.hansson@arm.com PortProxy physProxy; 2192520SN/A 2201885SN/A /** kernel symbol table */ 2211070SN/A SymbolTable *kernelSymtab; 222954SN/A 2231070SN/A /** Object pointer for the kernel code */ 2241070SN/A ObjectFile *kernel; 2251070SN/A 22612262Sandreas.sandberg@arm.com /** Additional object files */ 22712262Sandreas.sandberg@arm.com std::vector<ObjectFile *> kernelExtras; 22812262Sandreas.sandberg@arm.com 22911838SCurtis.Dunham@arm.com /** Beginning of kernel code */ 2301070SN/A Addr kernelStart; 2311070SN/A 2321070SN/A /** End of kernel code */ 2331070SN/A Addr kernelEnd; 2341070SN/A 2351070SN/A /** Entry point in the kernel to start at */ 2361070SN/A Addr kernelEntry; 2371070SN/A 2387580SAli.Saidi@arm.com /** Mask that should be anded for binary/symbol loading. 2397580SAli.Saidi@arm.com * This allows one two different OS requirements for the same ISA to be 2407580SAli.Saidi@arm.com * handled. Some OSes are compiled for a virtual address and need to be 2417580SAli.Saidi@arm.com * loaded into physical memory that starts at address 0, while other 2427580SAli.Saidi@arm.com * bare metal tools generate images that start at address 0. 2437580SAli.Saidi@arm.com */ 2447580SAli.Saidi@arm.com Addr loadAddrMask; 2457580SAli.Saidi@arm.com 24610037SARM gem5 Developers /** Offset that should be used for binary/symbol loading. 24711838SCurtis.Dunham@arm.com * This further allows more flexibility than the loadAddrMask allows alone 24811838SCurtis.Dunham@arm.com * in loading kernels and similar. The loadAddrOffset is applied after the 24910037SARM gem5 Developers * loadAddrMask. 25010037SARM gem5 Developers */ 25110037SARM gem5 Developers Addr loadAddrOffset; 25210037SARM gem5 Developers 2534997Sgblack@eecs.umich.edu public: 25411839SCurtis.Dunham@arm.com /** 25511839SCurtis.Dunham@arm.com * Get a pointer to the Kernel Virtual Machine (KVM) SimObject, 25611839SCurtis.Dunham@arm.com * if present. 25711839SCurtis.Dunham@arm.com */ 25811839SCurtis.Dunham@arm.com KvmVM* getKvmVM() { 25911839SCurtis.Dunham@arm.com return kvmVM; 26011839SCurtis.Dunham@arm.com } 26111839SCurtis.Dunham@arm.com 26212100SCurtis.Dunham@arm.com /** Verify gem5 configuration will support KVM emulation */ 26312100SCurtis.Dunham@arm.com bool validKvmEnvironment() const; 26412100SCurtis.Dunham@arm.com 2658931Sandreas.hansson@arm.com /** Get a pointer to access the physical memory of the system */ 2668931Sandreas.hansson@arm.com PhysicalMemory& getPhysMem() { return physmem; } 2678931Sandreas.hansson@arm.com 2685795Ssaidi@eecs.umich.edu /** Amount of physical memory that is still free */ 2698931Sandreas.hansson@arm.com Addr freeMemSize() const; 2705795Ssaidi@eecs.umich.edu 2715795Ssaidi@eecs.umich.edu /** Amount of physical memory that exists */ 2728931Sandreas.hansson@arm.com Addr memSize() const; 2738931Sandreas.hansson@arm.com 2748931Sandreas.hansson@arm.com /** 2758931Sandreas.hansson@arm.com * Check if a physical address is within a range of a memory that 2768931Sandreas.hansson@arm.com * is part of the global address map. 2778931Sandreas.hansson@arm.com * 2788931Sandreas.hansson@arm.com * @param addr A physical address 2798931Sandreas.hansson@arm.com * @return Whether the address corresponds to a memory 2808931Sandreas.hansson@arm.com */ 2818931Sandreas.hansson@arm.com bool isMemAddr(Addr addr) const; 2825795Ssaidi@eecs.umich.edu 28310467Sandreas.hansson@arm.com /** 28410467Sandreas.hansson@arm.com * Get the architecture. 28510467Sandreas.hansson@arm.com */ 28610467Sandreas.hansson@arm.com Arch getArch() const { return Arch::TheISA; } 28710467Sandreas.hansson@arm.com 28810466Sandreas.hansson@arm.com /** 28910466Sandreas.hansson@arm.com * Get the page bytes for the ISA. 29010466Sandreas.hansson@arm.com */ 29110466Sandreas.hansson@arm.com Addr getPageBytes() const { return TheISA::PageBytes; } 29210466Sandreas.hansson@arm.com 29310466Sandreas.hansson@arm.com /** 29411838SCurtis.Dunham@arm.com * Get the number of bits worth of in-page address for the ISA. 29510466Sandreas.hansson@arm.com */ 29610466Sandreas.hansson@arm.com Addr getPageShift() const { return TheISA::PageShift; } 29710466Sandreas.hansson@arm.com 29811420Sdavid.guillen@arm.com /** 29911420Sdavid.guillen@arm.com * The thermal model used for this system (if any). 30011420Sdavid.guillen@arm.com */ 30111420Sdavid.guillen@arm.com ThermalModel * getThermalModel() const { return thermalModel; } 30211420Sdavid.guillen@arm.com 3031885SN/A protected: 3048931Sandreas.hansson@arm.com 30511839SCurtis.Dunham@arm.com KvmVM *const kvmVM; 30611839SCurtis.Dunham@arm.com 3078931Sandreas.hansson@arm.com PhysicalMemory physmem; 3088931Sandreas.hansson@arm.com 3094762Snate@binkert.org Enums::MemoryMode memoryMode; 3109814Sandreas.hansson@arm.com 3119814Sandreas.hansson@arm.com const unsigned int _cacheLineSize; 3129814Sandreas.hansson@arm.com 3137914SBrad.Beckmann@amd.com uint64_t workItemsBegin; 3147914SBrad.Beckmann@amd.com uint64_t workItemsEnd; 3158666SPrakash.Ramrakhyani@arm.com uint32_t numWorkIds; 3167914SBrad.Beckmann@amd.com std::vector<bool> activeCpus; 3177914SBrad.Beckmann@amd.com 31811838SCurtis.Dunham@arm.com /** This array is a per-system list of all devices capable of issuing a 3198832SAli.Saidi@ARM.com * memory system request and an associated string for each master id. 3208832SAli.Saidi@ARM.com * It's used to uniquely id any master in the system by name for things 3218832SAli.Saidi@ARM.com * like cache statistics. 3228832SAli.Saidi@ARM.com */ 3238832SAli.Saidi@ARM.com std::vector<std::string> masterIds; 3248832SAli.Saidi@ARM.com 32511420Sdavid.guillen@arm.com ThermalModel * thermalModel; 32611420Sdavid.guillen@arm.com 3277914SBrad.Beckmann@amd.com public: 3288832SAli.Saidi@ARM.com 3298832SAli.Saidi@ARM.com /** Request an id used to create a request object in the system. All objects 3308832SAli.Saidi@ARM.com * that intend to issues requests into the memory system must request an id 3318832SAli.Saidi@ARM.com * in the init() phase of startup. All master ids must be fixed by the 33211838SCurtis.Dunham@arm.com * regStats() phase that immediately precedes it. This allows objects in 33311838SCurtis.Dunham@arm.com * the memory system to understand how many masters may exist and 3348832SAli.Saidi@ARM.com * appropriately name the bins of their per-master stats before the stats 3358832SAli.Saidi@ARM.com * are finalized 3368832SAli.Saidi@ARM.com */ 3378832SAli.Saidi@ARM.com MasterID getMasterId(std::string req_name); 3388832SAli.Saidi@ARM.com 3398832SAli.Saidi@ARM.com /** Get the name of an object for a given request id. 3408832SAli.Saidi@ARM.com */ 3418832SAli.Saidi@ARM.com std::string getMasterName(MasterID master_id); 3428832SAli.Saidi@ARM.com 3438832SAli.Saidi@ARM.com /** Get the number of masters registered in the system */ 3448832SAli.Saidi@ARM.com MasterID maxMasters() 3458832SAli.Saidi@ARM.com { 3468832SAli.Saidi@ARM.com return masterIds.size(); 3478832SAli.Saidi@ARM.com } 3488832SAli.Saidi@ARM.com 34911169Sandreas.hansson@arm.com void regStats() override; 3507914SBrad.Beckmann@amd.com /** 3517914SBrad.Beckmann@amd.com * Called by pseudo_inst to track the number of work items started by this 3527914SBrad.Beckmann@amd.com * system. 3537914SBrad.Beckmann@amd.com */ 3548666SPrakash.Ramrakhyani@arm.com uint64_t 3557914SBrad.Beckmann@amd.com incWorkItemsBegin() 3567914SBrad.Beckmann@amd.com { 3577914SBrad.Beckmann@amd.com return ++workItemsBegin; 3587914SBrad.Beckmann@amd.com } 3597914SBrad.Beckmann@amd.com 3607914SBrad.Beckmann@amd.com /** 3617914SBrad.Beckmann@amd.com * Called by pseudo_inst to track the number of work items completed by 3627914SBrad.Beckmann@amd.com * this system. 3637914SBrad.Beckmann@amd.com */ 36410037SARM gem5 Developers uint64_t 3657914SBrad.Beckmann@amd.com incWorkItemsEnd() 3667914SBrad.Beckmann@amd.com { 3677914SBrad.Beckmann@amd.com return ++workItemsEnd; 3687914SBrad.Beckmann@amd.com } 3697914SBrad.Beckmann@amd.com 3707914SBrad.Beckmann@amd.com /** 3717914SBrad.Beckmann@amd.com * Called by pseudo_inst to mark the cpus actively executing work items. 3727914SBrad.Beckmann@amd.com * Returns the total number of cpus that have executed work item begin or 3737914SBrad.Beckmann@amd.com * ends. 3747914SBrad.Beckmann@amd.com */ 37510037SARM gem5 Developers int 3767914SBrad.Beckmann@amd.com markWorkItem(int index) 3777914SBrad.Beckmann@amd.com { 3787914SBrad.Beckmann@amd.com int count = 0; 3797914SBrad.Beckmann@amd.com assert(index < activeCpus.size()); 3807914SBrad.Beckmann@amd.com activeCpus[index] = true; 38110037SARM gem5 Developers for (std::vector<bool>::iterator i = activeCpus.begin(); 3827914SBrad.Beckmann@amd.com i < activeCpus.end(); i++) { 3837914SBrad.Beckmann@amd.com if (*i) count++; 3847914SBrad.Beckmann@amd.com } 3857914SBrad.Beckmann@amd.com return count; 3867914SBrad.Beckmann@amd.com } 3872901Ssaidi@eecs.umich.edu 3888666SPrakash.Ramrakhyani@arm.com inline void workItemBegin(uint32_t tid, uint32_t workid) 3898666SPrakash.Ramrakhyani@arm.com { 3908666SPrakash.Ramrakhyani@arm.com std::pair<uint32_t,uint32_t> p(tid, workid); 3918666SPrakash.Ramrakhyani@arm.com lastWorkItemStarted[p] = curTick(); 3928666SPrakash.Ramrakhyani@arm.com } 3938666SPrakash.Ramrakhyani@arm.com 3948666SPrakash.Ramrakhyani@arm.com void workItemEnd(uint32_t tid, uint32_t workid); 3958666SPrakash.Ramrakhyani@arm.com 3961885SN/A /** 3971885SN/A * Fix up an address used to match PCs for hooking simulator 3981885SN/A * events on to target function executions. See comment in 3991885SN/A * system.cc for details. 4001885SN/A */ 4018769Sgblack@eecs.umich.edu virtual Addr fixFuncEventAddr(Addr addr) 4028769Sgblack@eecs.umich.edu { 4038769Sgblack@eecs.umich.edu panic("Base fixFuncEventAddr not implemented.\n"); 4048769Sgblack@eecs.umich.edu } 4051885SN/A 4069645SAndreas.Sandberg@ARM.com /** @{ */ 4071885SN/A /** 4081885SN/A * Add a function-based event to the given function, to be looked 4091885SN/A * up in the specified symbol table. 4109645SAndreas.Sandberg@ARM.com * 4119645SAndreas.Sandberg@ARM.com * The ...OrPanic flavor of the method causes the simulator to 4129645SAndreas.Sandberg@ARM.com * panic if the symbol can't be found. 4139645SAndreas.Sandberg@ARM.com * 4149645SAndreas.Sandberg@ARM.com * @param symtab Symbol table to use for look up. 4159645SAndreas.Sandberg@ARM.com * @param lbl Function to hook the event to. 4169645SAndreas.Sandberg@ARM.com * @param desc Description to be passed to the event. 4179645SAndreas.Sandberg@ARM.com * @param args Arguments to be forwarded to the event constructor. 4181885SN/A */ 4199645SAndreas.Sandberg@ARM.com template <class T, typename... Args> 4209645SAndreas.Sandberg@ARM.com T *addFuncEvent(const SymbolTable *symtab, const char *lbl, 4219645SAndreas.Sandberg@ARM.com const std::string &desc, Args... args) 4221885SN/A { 4239855Sandreas.hansson@arm.com Addr addr M5_VAR_USED = 0; // initialize only to avoid compiler warning 4241885SN/A 4259850Sandreas.hansson@arm.com#if THE_ISA != NULL_ISA 4261885SN/A if (symtab->findAddress(lbl, addr)) { 4279645SAndreas.Sandberg@ARM.com T *ev = new T(&pcEventQueue, desc, fixFuncEventAddr(addr), 4289645SAndreas.Sandberg@ARM.com std::forward<Args>(args)...); 4291885SN/A return ev; 4301885SN/A } 4319850Sandreas.hansson@arm.com#endif 4321885SN/A 4331885SN/A return NULL; 4341885SN/A } 4351885SN/A 4361885SN/A template <class T> 4379645SAndreas.Sandberg@ARM.com T *addFuncEvent(const SymbolTable *symtab, const char *lbl) 4381885SN/A { 4399645SAndreas.Sandberg@ARM.com return addFuncEvent<T>(symtab, lbl, lbl); 4401885SN/A } 4411885SN/A 4429645SAndreas.Sandberg@ARM.com template <class T, typename... Args> 4439645SAndreas.Sandberg@ARM.com T *addFuncEventOrPanic(const SymbolTable *symtab, const char *lbl, 4449645SAndreas.Sandberg@ARM.com Args... args) 4459645SAndreas.Sandberg@ARM.com { 4469645SAndreas.Sandberg@ARM.com T *e(addFuncEvent<T>(symtab, lbl, std::forward<Args>(args)...)); 4479645SAndreas.Sandberg@ARM.com if (!e) 4489645SAndreas.Sandberg@ARM.com panic("Failed to find symbol '%s'", lbl); 4499645SAndreas.Sandberg@ARM.com return e; 4509645SAndreas.Sandberg@ARM.com } 4519645SAndreas.Sandberg@ARM.com /** @} */ 4529645SAndreas.Sandberg@ARM.com 4539645SAndreas.Sandberg@ARM.com /** @{ */ 4549645SAndreas.Sandberg@ARM.com /** 4559645SAndreas.Sandberg@ARM.com * Add a function-based event to a kernel symbol. 4569645SAndreas.Sandberg@ARM.com * 4579645SAndreas.Sandberg@ARM.com * These functions work like their addFuncEvent() and 4589645SAndreas.Sandberg@ARM.com * addFuncEventOrPanic() counterparts. The only difference is that 4599645SAndreas.Sandberg@ARM.com * they automatically use the kernel symbol table. All arguments 4609645SAndreas.Sandberg@ARM.com * are forwarded to the underlying method. 4619645SAndreas.Sandberg@ARM.com * 4629645SAndreas.Sandberg@ARM.com * @see addFuncEvent() 4639645SAndreas.Sandberg@ARM.com * @see addFuncEventOrPanic() 4649645SAndreas.Sandberg@ARM.com * 4659645SAndreas.Sandberg@ARM.com * @param lbl Function to hook the event to. 4669645SAndreas.Sandberg@ARM.com * @param args Arguments to be passed to addFuncEvent 4679645SAndreas.Sandberg@ARM.com */ 4689645SAndreas.Sandberg@ARM.com template <class T, typename... Args> 4699645SAndreas.Sandberg@ARM.com T *addKernelFuncEvent(const char *lbl, Args... args) 4709645SAndreas.Sandberg@ARM.com { 4719645SAndreas.Sandberg@ARM.com return addFuncEvent<T>(kernelSymtab, lbl, 4729645SAndreas.Sandberg@ARM.com std::forward<Args>(args)...); 4739645SAndreas.Sandberg@ARM.com } 4749645SAndreas.Sandberg@ARM.com 4759645SAndreas.Sandberg@ARM.com template <class T, typename... Args> 4769645SAndreas.Sandberg@ARM.com T *addKernelFuncEventOrPanic(const char *lbl, Args... args) 4779645SAndreas.Sandberg@ARM.com { 4789645SAndreas.Sandberg@ARM.com T *e(addFuncEvent<T>(kernelSymtab, lbl, 4799645SAndreas.Sandberg@ARM.com std::forward<Args>(args)...)); 4809645SAndreas.Sandberg@ARM.com if (!e) 4819645SAndreas.Sandberg@ARM.com panic("Failed to find kernel symbol '%s'", lbl); 4829645SAndreas.Sandberg@ARM.com return e; 4839645SAndreas.Sandberg@ARM.com } 4849645SAndreas.Sandberg@ARM.com /** @} */ 4859645SAndreas.Sandberg@ARM.com 48677SN/A public: 4876658Snate@binkert.org std::vector<BaseRemoteGDB *> remoteGDB; 4883960Sgblack@eecs.umich.edu bool breakpoint(); 4891070SN/A 4901070SN/A public: 4914762Snate@binkert.org typedef SystemParams Params; 4921070SN/A 4932158SN/A protected: 4942158SN/A Params *_params; 4951070SN/A 4962158SN/A public: 4971070SN/A System(Params *p); 4982SN/A ~System(); 4992SN/A 50011169Sandreas.hansson@arm.com void initState() override; 5011129SN/A 5022158SN/A const Params *params() const { return (const Params *)_params; } 5032158SN/A 5041070SN/A public: 5052378SN/A 5061070SN/A /** 50711838SCurtis.Dunham@arm.com * Returns the address the kernel starts at. 5081070SN/A * @return address the kernel starts at 5091070SN/A */ 5101070SN/A Addr getKernelStart() const { return kernelStart; } 5111070SN/A 5121070SN/A /** 51311838SCurtis.Dunham@arm.com * Returns the address the kernel ends at. 5141070SN/A * @return address the kernel ends at 5151070SN/A */ 5161070SN/A Addr getKernelEnd() const { return kernelEnd; } 5171070SN/A 5181070SN/A /** 51911838SCurtis.Dunham@arm.com * Returns the address the entry point to the kernel code. 5201070SN/A * @return entry point of the kernel code 5211070SN/A */ 5221070SN/A Addr getKernelEntry() const { return kernelEntry; } 5231070SN/A 5248601Ssteve.reinhardt@amd.com /// Allocate npages contiguous unused physical pages 5258601Ssteve.reinhardt@amd.com /// @return Starting address of first page 5268601Ssteve.reinhardt@amd.com Addr allocPhysPages(int npages); 5272378SN/A 52811005Sandreas.sandberg@arm.com ContextID registerThreadContext(ThreadContext *tc, 52911005Sandreas.sandberg@arm.com ContextID assigned = InvalidContextID); 53011005Sandreas.sandberg@arm.com void replaceThreadContext(ThreadContext *tc, ContextID context_id); 5311070SN/A 53211168Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 53311168Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 5349342SAndreas.Sandberg@arm.com 53511168Sandreas.hansson@arm.com void drainResume() override; 5362SN/A 53777SN/A public: 5387897Shestness@cs.utexas.edu Counter totalNumInsts; 5397897Shestness@cs.utexas.edu EventQueue instEventQueue; 5408666SPrakash.Ramrakhyani@arm.com std::map<std::pair<uint32_t,uint32_t>, Tick> lastWorkItemStarted; 5418666SPrakash.Ramrakhyani@arm.com std::map<uint32_t, Stats::Histogram*> workItemStats; 5427897Shestness@cs.utexas.edu 5432SN/A //////////////////////////////////////////// 5442SN/A // 5452SN/A // STATIC GLOBAL SYSTEM LIST 5462SN/A // 5472SN/A //////////////////////////////////////////// 5482SN/A 5492SN/A static std::vector<System *> systemList; 5502SN/A static int numSystemsRunning; 5512SN/A 5522SN/A static void printSystems(); 5532158SN/A 55411911SBrandon.Potter@amd.com FutexMap futexMap; 5559112Smarc.orr@gmail.com 55611885Sbrandon.potter@amd.com static const int maxPID = 32768; 55711885Sbrandon.potter@amd.com 55811885Sbrandon.potter@amd.com /** Process set to track which PIDs have already been allocated */ 55911885Sbrandon.potter@amd.com std::set<int> PIDs; 56011885Sbrandon.potter@amd.com 56111909SBrandon.Potter@amd.com // By convention, all signals are owned by the receiving process. The 56211909SBrandon.Potter@amd.com // receiver will delete the signal upon reception. 56311909SBrandon.Potter@amd.com std::list<BasicSignal> signalList; 56411909SBrandon.Potter@amd.com 5659292Sandreas.hansson@arm.com protected: 5669292Sandreas.hansson@arm.com 5679292Sandreas.hansson@arm.com /** 5689292Sandreas.hansson@arm.com * If needed, serialize additional symbol table entries for a 56911838SCurtis.Dunham@arm.com * specific subclass of this system. Currently this is used by 5709292Sandreas.hansson@arm.com * Alpha and MIPS. 5719292Sandreas.hansson@arm.com * 5729292Sandreas.hansson@arm.com * @param os stream to serialize to 5739292Sandreas.hansson@arm.com */ 57410905Sandreas.sandberg@arm.com virtual void serializeSymtab(CheckpointOut &os) const {} 5759292Sandreas.hansson@arm.com 5769292Sandreas.hansson@arm.com /** 5779292Sandreas.hansson@arm.com * If needed, unserialize additional symbol table entries for a 5789292Sandreas.hansson@arm.com * specific subclass of this system. 5799292Sandreas.hansson@arm.com * 5809292Sandreas.hansson@arm.com * @param cp checkpoint to unserialize from 5819292Sandreas.hansson@arm.com * @param section relevant section in the checkpoint 5829292Sandreas.hansson@arm.com */ 58310905Sandreas.sandberg@arm.com virtual void unserializeSymtab(CheckpointIn &cp) {} 5842158SN/A 5852SN/A}; 5862SN/A 5879554Sandreas.hansson@arm.comvoid printSystems(); 5889554Sandreas.hansson@arm.com 5892SN/A#endif // __SYSTEM_HH__ 590