system.hh revision 12100
12SN/A/* 210466Sandreas.hansson@arm.com * Copyright (c) 2012, 2014 ARM Limited 38703Sandreas.hansson@arm.com * All rights reserved 48703Sandreas.hansson@arm.com * 58703Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68703Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78703Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88703Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98703Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108703Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118703Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128703Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138703Sandreas.hansson@arm.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422665Ssaidi@eecs.umich.edu * Lisa Hsu 432665Ssaidi@eecs.umich.edu * Nathan Binkert 447897Shestness@cs.utexas.edu * Rick Strong 452SN/A */ 462SN/A 472SN/A#ifndef __SYSTEM_HH__ 482SN/A#define __SYSTEM_HH__ 492SN/A 502SN/A#include <string> 5111911SBrandon.Potter@amd.com#include <unordered_map> 529645SAndreas.Sandberg@ARM.com#include <utility> 5375SN/A#include <vector> 542SN/A 5510466Sandreas.hansson@arm.com#include "arch/isa_traits.hh" 562439SN/A#include "base/loader/symtab.hh" 57603SN/A#include "base/statistics.hh" 5810466Sandreas.hansson@arm.com#include "config/the_isa.hh" 594762Snate@binkert.org#include "enums/MemoryMode.hh" 608703Sandreas.hansson@arm.com#include "mem/mem_object.hh" 6111911SBrandon.Potter@amd.com#include "mem/physical.hh" 622520SN/A#include "mem/port.hh" 639847Sandreas.hansson@arm.com#include "mem/port_proxy.hh" 644762Snate@binkert.org#include "params/System.hh" 6511911SBrandon.Potter@amd.com#include "sim/futex_map.hh" 6611909SBrandon.Potter@amd.com#include "sim/se_signal.hh" 676658Snate@binkert.org 6810494Sandreas.hansson@arm.com/** 6910494Sandreas.hansson@arm.com * To avoid linking errors with LTO, only include the header if we 7010494Sandreas.hansson@arm.com * actually have the definition. 7110494Sandreas.hansson@arm.com */ 7210494Sandreas.hansson@arm.com#if THE_ISA != NULL_ISA 7310494Sandreas.hansson@arm.com#include "cpu/pc_event.hh" 7411911SBrandon.Potter@amd.com 7510494Sandreas.hansson@arm.com#endif 7610494Sandreas.hansson@arm.com 778769Sgblack@eecs.umich.educlass BaseRemoteGDB; 788769Sgblack@eecs.umich.educlass GDBListener; 7911839SCurtis.Dunham@arm.comclass KvmVM; 801634SN/Aclass ObjectFile; 818769Sgblack@eecs.umich.educlass ThreadContext; 822SN/A 838703Sandreas.hansson@arm.comclass System : public MemObject 842SN/A{ 858703Sandreas.hansson@arm.com private: 868703Sandreas.hansson@arm.com 878703Sandreas.hansson@arm.com /** 888703Sandreas.hansson@arm.com * Private class for the system port which is only used as a 898703Sandreas.hansson@arm.com * master for debug access and for non-structural entities that do 908703Sandreas.hansson@arm.com * not have a port of their own. 918703Sandreas.hansson@arm.com */ 928922Swilliam.wang@arm.com class SystemPort : public MasterPort 938703Sandreas.hansson@arm.com { 948703Sandreas.hansson@arm.com public: 958703Sandreas.hansson@arm.com 968703Sandreas.hansson@arm.com /** 978703Sandreas.hansson@arm.com * Create a system port with a name and an owner. 988703Sandreas.hansson@arm.com */ 998703Sandreas.hansson@arm.com SystemPort(const std::string &_name, MemObject *_owner) 1008922Swilliam.wang@arm.com : MasterPort(_name, _owner) 1018703Sandreas.hansson@arm.com { } 10211169Sandreas.hansson@arm.com bool recvTimingResp(PacketPtr pkt) override 1038703Sandreas.hansson@arm.com { panic("SystemPort does not receive timing!\n"); return false; } 10411169Sandreas.hansson@arm.com void recvReqRetry() override 1058922Swilliam.wang@arm.com { panic("SystemPort does not expect retry!\n"); } 1068703Sandreas.hansson@arm.com }; 1078703Sandreas.hansson@arm.com 1088703Sandreas.hansson@arm.com SystemPort _systemPort; 1098703Sandreas.hansson@arm.com 110603SN/A public: 1112901Ssaidi@eecs.umich.edu 1128703Sandreas.hansson@arm.com /** 1138706Sandreas.hansson@arm.com * After all objects have been created and all ports are 1148706Sandreas.hansson@arm.com * connected, check that the system port is connected. 1158706Sandreas.hansson@arm.com */ 11611169Sandreas.hansson@arm.com void init() override; 1178706Sandreas.hansson@arm.com 1188706Sandreas.hansson@arm.com /** 1198852Sandreas.hansson@arm.com * Get a reference to the system port that can be used by 1208703Sandreas.hansson@arm.com * non-structural simulation objects like processes or threads, or 1218703Sandreas.hansson@arm.com * external entities like loaders and debuggers, etc, to access 1228703Sandreas.hansson@arm.com * the memory system. 1238703Sandreas.hansson@arm.com * 1248852Sandreas.hansson@arm.com * @return a reference to the system port we own 1258703Sandreas.hansson@arm.com */ 1268922Swilliam.wang@arm.com MasterPort& getSystemPort() { return _systemPort; } 1278703Sandreas.hansson@arm.com 1288703Sandreas.hansson@arm.com /** 1298703Sandreas.hansson@arm.com * Additional function to return the Port of a memory object. 1308703Sandreas.hansson@arm.com */ 1319294Sandreas.hansson@arm.com BaseMasterPort& getMasterPort(const std::string &if_name, 13211169Sandreas.hansson@arm.com PortID idx = InvalidPortID) override; 1338703Sandreas.hansson@arm.com 1349524SAndreas.Sandberg@ARM.com /** @{ */ 1359524SAndreas.Sandberg@ARM.com /** 1369524SAndreas.Sandberg@ARM.com * Is the system in atomic mode? 1379524SAndreas.Sandberg@ARM.com * 1389524SAndreas.Sandberg@ARM.com * There are currently two different atomic memory modes: 1399524SAndreas.Sandberg@ARM.com * 'atomic', which supports caches; and 'atomic_noncaching', which 1409524SAndreas.Sandberg@ARM.com * bypasses caches. The latter is used by hardware virtualized 1419524SAndreas.Sandberg@ARM.com * CPUs. SimObjects are expected to use Port::sendAtomic() and 1429524SAndreas.Sandberg@ARM.com * Port::recvAtomic() when accessing memory in this mode. 1439524SAndreas.Sandberg@ARM.com */ 1449524SAndreas.Sandberg@ARM.com bool isAtomicMode() const { 1459524SAndreas.Sandberg@ARM.com return memoryMode == Enums::atomic || 1469524SAndreas.Sandberg@ARM.com memoryMode == Enums::atomic_noncaching; 1474762Snate@binkert.org } 1482901Ssaidi@eecs.umich.edu 1499524SAndreas.Sandberg@ARM.com /** 1509524SAndreas.Sandberg@ARM.com * Is the system in timing mode? 1519524SAndreas.Sandberg@ARM.com * 1529524SAndreas.Sandberg@ARM.com * SimObjects are expected to use Port::sendTiming() and 1539524SAndreas.Sandberg@ARM.com * Port::recvTiming() when accessing memory in this mode. 1549524SAndreas.Sandberg@ARM.com */ 1559524SAndreas.Sandberg@ARM.com bool isTimingMode() const { 1569524SAndreas.Sandberg@ARM.com return memoryMode == Enums::timing; 1579524SAndreas.Sandberg@ARM.com } 1589524SAndreas.Sandberg@ARM.com 1599524SAndreas.Sandberg@ARM.com /** 1609524SAndreas.Sandberg@ARM.com * Should caches be bypassed? 1619524SAndreas.Sandberg@ARM.com * 1629524SAndreas.Sandberg@ARM.com * Some CPUs need to bypass caches to allow direct memory 1639524SAndreas.Sandberg@ARM.com * accesses, which is required for hardware virtualization. 1649524SAndreas.Sandberg@ARM.com */ 1659524SAndreas.Sandberg@ARM.com bool bypassCaches() const { 1669524SAndreas.Sandberg@ARM.com return memoryMode == Enums::atomic_noncaching; 1679524SAndreas.Sandberg@ARM.com } 1689524SAndreas.Sandberg@ARM.com /** @} */ 1699524SAndreas.Sandberg@ARM.com 1709524SAndreas.Sandberg@ARM.com /** @{ */ 1719524SAndreas.Sandberg@ARM.com /** 1729524SAndreas.Sandberg@ARM.com * Get the memory mode of the system. 1739524SAndreas.Sandberg@ARM.com * 1749524SAndreas.Sandberg@ARM.com * \warn This should only be used by the Python world. The C++ 1759524SAndreas.Sandberg@ARM.com * world should use one of the query functions above 1769524SAndreas.Sandberg@ARM.com * (isAtomicMode(), isTimingMode(), bypassCaches()). 1779524SAndreas.Sandberg@ARM.com */ 1789524SAndreas.Sandberg@ARM.com Enums::MemoryMode getMemoryMode() const { return memoryMode; } 1799524SAndreas.Sandberg@ARM.com 1809524SAndreas.Sandberg@ARM.com /** 1819524SAndreas.Sandberg@ARM.com * Change the memory mode of the system. 1829524SAndreas.Sandberg@ARM.com * 1839524SAndreas.Sandberg@ARM.com * \warn This should only be called by the Python! 1849524SAndreas.Sandberg@ARM.com * 1859524SAndreas.Sandberg@ARM.com * @param mode Mode to change to (atomic/timing/...) 1862901Ssaidi@eecs.umich.edu */ 1874762Snate@binkert.org void setMemoryMode(Enums::MemoryMode mode); 1889524SAndreas.Sandberg@ARM.com /** @} */ 1892901Ssaidi@eecs.umich.edu 1909814Sandreas.hansson@arm.com /** 1919814Sandreas.hansson@arm.com * Get the cache line size of the system. 1929814Sandreas.hansson@arm.com */ 1939814Sandreas.hansson@arm.com unsigned int cacheLineSize() const { return _cacheLineSize; } 1949814Sandreas.hansson@arm.com 1959850Sandreas.hansson@arm.com#if THE_ISA != NULL_ISA 1962SN/A PCEventQueue pcEventQueue; 1979850Sandreas.hansson@arm.com#endif 1982SN/A 1992680Sktlim@umich.edu std::vector<ThreadContext *> threadContexts; 2005714Shsul@eecs.umich.edu int _numContexts; 20111146Smitch.hayenga@arm.com const bool multiThread; 2021806SN/A 20311005Sandreas.sandberg@arm.com ThreadContext *getThreadContext(ContextID tid) 2045713Shsul@eecs.umich.edu { 2055713Shsul@eecs.umich.edu return threadContexts[tid]; 2065713Shsul@eecs.umich.edu } 2075713Shsul@eecs.umich.edu 2085714Shsul@eecs.umich.edu int numContexts() 2091806SN/A { 2106227Snate@binkert.org assert(_numContexts == (int)threadContexts.size()); 2115714Shsul@eecs.umich.edu return _numContexts; 2121806SN/A } 213180SN/A 2146029Ssteve.reinhardt@amd.com /** Return number of running (non-halted) thread contexts in 2156029Ssteve.reinhardt@amd.com * system. These threads could be Active or Suspended. */ 2166029Ssteve.reinhardt@amd.com int numRunningContexts(); 2176029Ssteve.reinhardt@amd.com 2188765Sgblack@eecs.umich.edu Addr pagePtr; 2198765Sgblack@eecs.umich.edu 2202378SN/A uint64_t init_param; 2212378SN/A 2222520SN/A /** Port to physical memory used for writing object files into ram at 2232520SN/A * boot.*/ 2248852Sandreas.hansson@arm.com PortProxy physProxy; 2252520SN/A 2261885SN/A /** kernel symbol table */ 2271070SN/A SymbolTable *kernelSymtab; 228954SN/A 2291070SN/A /** Object pointer for the kernel code */ 2301070SN/A ObjectFile *kernel; 2311070SN/A 23211838SCurtis.Dunham@arm.com /** Beginning of kernel code */ 2331070SN/A Addr kernelStart; 2341070SN/A 2351070SN/A /** End of kernel code */ 2361070SN/A Addr kernelEnd; 2371070SN/A 2381070SN/A /** Entry point in the kernel to start at */ 2391070SN/A Addr kernelEntry; 2401070SN/A 2417580SAli.Saidi@arm.com /** Mask that should be anded for binary/symbol loading. 2427580SAli.Saidi@arm.com * This allows one two different OS requirements for the same ISA to be 2437580SAli.Saidi@arm.com * handled. Some OSes are compiled for a virtual address and need to be 2447580SAli.Saidi@arm.com * loaded into physical memory that starts at address 0, while other 2457580SAli.Saidi@arm.com * bare metal tools generate images that start at address 0. 2467580SAli.Saidi@arm.com */ 2477580SAli.Saidi@arm.com Addr loadAddrMask; 2487580SAli.Saidi@arm.com 24910037SARM gem5 Developers /** Offset that should be used for binary/symbol loading. 25011838SCurtis.Dunham@arm.com * This further allows more flexibility than the loadAddrMask allows alone 25111838SCurtis.Dunham@arm.com * in loading kernels and similar. The loadAddrOffset is applied after the 25210037SARM gem5 Developers * loadAddrMask. 25310037SARM gem5 Developers */ 25410037SARM gem5 Developers Addr loadAddrOffset; 25510037SARM gem5 Developers 2564997Sgblack@eecs.umich.edu public: 25711839SCurtis.Dunham@arm.com /** 25811839SCurtis.Dunham@arm.com * Get a pointer to the Kernel Virtual Machine (KVM) SimObject, 25911839SCurtis.Dunham@arm.com * if present. 26011839SCurtis.Dunham@arm.com */ 26111839SCurtis.Dunham@arm.com KvmVM* getKvmVM() { 26211839SCurtis.Dunham@arm.com return kvmVM; 26311839SCurtis.Dunham@arm.com } 26411839SCurtis.Dunham@arm.com 26512100SCurtis.Dunham@arm.com /** Verify gem5 configuration will support KVM emulation */ 26612100SCurtis.Dunham@arm.com bool validKvmEnvironment() const; 26712100SCurtis.Dunham@arm.com 2688931Sandreas.hansson@arm.com /** Get a pointer to access the physical memory of the system */ 2698931Sandreas.hansson@arm.com PhysicalMemory& getPhysMem() { return physmem; } 2708931Sandreas.hansson@arm.com 2715795Ssaidi@eecs.umich.edu /** Amount of physical memory that is still free */ 2728931Sandreas.hansson@arm.com Addr freeMemSize() const; 2735795Ssaidi@eecs.umich.edu 2745795Ssaidi@eecs.umich.edu /** Amount of physical memory that exists */ 2758931Sandreas.hansson@arm.com Addr memSize() const; 2768931Sandreas.hansson@arm.com 2778931Sandreas.hansson@arm.com /** 2788931Sandreas.hansson@arm.com * Check if a physical address is within a range of a memory that 2798931Sandreas.hansson@arm.com * is part of the global address map. 2808931Sandreas.hansson@arm.com * 2818931Sandreas.hansson@arm.com * @param addr A physical address 2828931Sandreas.hansson@arm.com * @return Whether the address corresponds to a memory 2838931Sandreas.hansson@arm.com */ 2848931Sandreas.hansson@arm.com bool isMemAddr(Addr addr) const; 2855795Ssaidi@eecs.umich.edu 28610467Sandreas.hansson@arm.com /** 28710467Sandreas.hansson@arm.com * Get the architecture. 28810467Sandreas.hansson@arm.com */ 28910467Sandreas.hansson@arm.com Arch getArch() const { return Arch::TheISA; } 29010467Sandreas.hansson@arm.com 29110466Sandreas.hansson@arm.com /** 29210466Sandreas.hansson@arm.com * Get the page bytes for the ISA. 29310466Sandreas.hansson@arm.com */ 29410466Sandreas.hansson@arm.com Addr getPageBytes() const { return TheISA::PageBytes; } 29510466Sandreas.hansson@arm.com 29610466Sandreas.hansson@arm.com /** 29711838SCurtis.Dunham@arm.com * Get the number of bits worth of in-page address for the ISA. 29810466Sandreas.hansson@arm.com */ 29910466Sandreas.hansson@arm.com Addr getPageShift() const { return TheISA::PageShift; } 30010466Sandreas.hansson@arm.com 30111420Sdavid.guillen@arm.com /** 30211420Sdavid.guillen@arm.com * The thermal model used for this system (if any). 30311420Sdavid.guillen@arm.com */ 30411420Sdavid.guillen@arm.com ThermalModel * getThermalModel() const { return thermalModel; } 30511420Sdavid.guillen@arm.com 3061885SN/A protected: 3078931Sandreas.hansson@arm.com 30811839SCurtis.Dunham@arm.com KvmVM *const kvmVM; 30911839SCurtis.Dunham@arm.com 3108931Sandreas.hansson@arm.com PhysicalMemory physmem; 3118931Sandreas.hansson@arm.com 3124762Snate@binkert.org Enums::MemoryMode memoryMode; 3139814Sandreas.hansson@arm.com 3149814Sandreas.hansson@arm.com const unsigned int _cacheLineSize; 3159814Sandreas.hansson@arm.com 3167914SBrad.Beckmann@amd.com uint64_t workItemsBegin; 3177914SBrad.Beckmann@amd.com uint64_t workItemsEnd; 3188666SPrakash.Ramrakhyani@arm.com uint32_t numWorkIds; 3197914SBrad.Beckmann@amd.com std::vector<bool> activeCpus; 3207914SBrad.Beckmann@amd.com 32111838SCurtis.Dunham@arm.com /** This array is a per-system list of all devices capable of issuing a 3228832SAli.Saidi@ARM.com * memory system request and an associated string for each master id. 3238832SAli.Saidi@ARM.com * It's used to uniquely id any master in the system by name for things 3248832SAli.Saidi@ARM.com * like cache statistics. 3258832SAli.Saidi@ARM.com */ 3268832SAli.Saidi@ARM.com std::vector<std::string> masterIds; 3278832SAli.Saidi@ARM.com 32811420Sdavid.guillen@arm.com ThermalModel * thermalModel; 32911420Sdavid.guillen@arm.com 3307914SBrad.Beckmann@amd.com public: 3318832SAli.Saidi@ARM.com 3328832SAli.Saidi@ARM.com /** Request an id used to create a request object in the system. All objects 3338832SAli.Saidi@ARM.com * that intend to issues requests into the memory system must request an id 3348832SAli.Saidi@ARM.com * in the init() phase of startup. All master ids must be fixed by the 33511838SCurtis.Dunham@arm.com * regStats() phase that immediately precedes it. This allows objects in 33611838SCurtis.Dunham@arm.com * the memory system to understand how many masters may exist and 3378832SAli.Saidi@ARM.com * appropriately name the bins of their per-master stats before the stats 3388832SAli.Saidi@ARM.com * are finalized 3398832SAli.Saidi@ARM.com */ 3408832SAli.Saidi@ARM.com MasterID getMasterId(std::string req_name); 3418832SAli.Saidi@ARM.com 3428832SAli.Saidi@ARM.com /** Get the name of an object for a given request id. 3438832SAli.Saidi@ARM.com */ 3448832SAli.Saidi@ARM.com std::string getMasterName(MasterID master_id); 3458832SAli.Saidi@ARM.com 3468832SAli.Saidi@ARM.com /** Get the number of masters registered in the system */ 3478832SAli.Saidi@ARM.com MasterID maxMasters() 3488832SAli.Saidi@ARM.com { 3498832SAli.Saidi@ARM.com return masterIds.size(); 3508832SAli.Saidi@ARM.com } 3518832SAli.Saidi@ARM.com 35211169Sandreas.hansson@arm.com void regStats() override; 3537914SBrad.Beckmann@amd.com /** 3547914SBrad.Beckmann@amd.com * Called by pseudo_inst to track the number of work items started by this 3557914SBrad.Beckmann@amd.com * system. 3567914SBrad.Beckmann@amd.com */ 3578666SPrakash.Ramrakhyani@arm.com uint64_t 3587914SBrad.Beckmann@amd.com incWorkItemsBegin() 3597914SBrad.Beckmann@amd.com { 3607914SBrad.Beckmann@amd.com return ++workItemsBegin; 3617914SBrad.Beckmann@amd.com } 3627914SBrad.Beckmann@amd.com 3637914SBrad.Beckmann@amd.com /** 3647914SBrad.Beckmann@amd.com * Called by pseudo_inst to track the number of work items completed by 3657914SBrad.Beckmann@amd.com * this system. 3667914SBrad.Beckmann@amd.com */ 36710037SARM gem5 Developers uint64_t 3687914SBrad.Beckmann@amd.com incWorkItemsEnd() 3697914SBrad.Beckmann@amd.com { 3707914SBrad.Beckmann@amd.com return ++workItemsEnd; 3717914SBrad.Beckmann@amd.com } 3727914SBrad.Beckmann@amd.com 3737914SBrad.Beckmann@amd.com /** 3747914SBrad.Beckmann@amd.com * Called by pseudo_inst to mark the cpus actively executing work items. 3757914SBrad.Beckmann@amd.com * Returns the total number of cpus that have executed work item begin or 3767914SBrad.Beckmann@amd.com * ends. 3777914SBrad.Beckmann@amd.com */ 37810037SARM gem5 Developers int 3797914SBrad.Beckmann@amd.com markWorkItem(int index) 3807914SBrad.Beckmann@amd.com { 3817914SBrad.Beckmann@amd.com int count = 0; 3827914SBrad.Beckmann@amd.com assert(index < activeCpus.size()); 3837914SBrad.Beckmann@amd.com activeCpus[index] = true; 38410037SARM gem5 Developers for (std::vector<bool>::iterator i = activeCpus.begin(); 3857914SBrad.Beckmann@amd.com i < activeCpus.end(); i++) { 3867914SBrad.Beckmann@amd.com if (*i) count++; 3877914SBrad.Beckmann@amd.com } 3887914SBrad.Beckmann@amd.com return count; 3897914SBrad.Beckmann@amd.com } 3902901Ssaidi@eecs.umich.edu 3918666SPrakash.Ramrakhyani@arm.com inline void workItemBegin(uint32_t tid, uint32_t workid) 3928666SPrakash.Ramrakhyani@arm.com { 3938666SPrakash.Ramrakhyani@arm.com std::pair<uint32_t,uint32_t> p(tid, workid); 3948666SPrakash.Ramrakhyani@arm.com lastWorkItemStarted[p] = curTick(); 3958666SPrakash.Ramrakhyani@arm.com } 3968666SPrakash.Ramrakhyani@arm.com 3978666SPrakash.Ramrakhyani@arm.com void workItemEnd(uint32_t tid, uint32_t workid); 3988666SPrakash.Ramrakhyani@arm.com 3991885SN/A /** 4001885SN/A * Fix up an address used to match PCs for hooking simulator 4011885SN/A * events on to target function executions. See comment in 4021885SN/A * system.cc for details. 4031885SN/A */ 4048769Sgblack@eecs.umich.edu virtual Addr fixFuncEventAddr(Addr addr) 4058769Sgblack@eecs.umich.edu { 4068769Sgblack@eecs.umich.edu panic("Base fixFuncEventAddr not implemented.\n"); 4078769Sgblack@eecs.umich.edu } 4081885SN/A 4099645SAndreas.Sandberg@ARM.com /** @{ */ 4101885SN/A /** 4111885SN/A * Add a function-based event to the given function, to be looked 4121885SN/A * up in the specified symbol table. 4139645SAndreas.Sandberg@ARM.com * 4149645SAndreas.Sandberg@ARM.com * The ...OrPanic flavor of the method causes the simulator to 4159645SAndreas.Sandberg@ARM.com * panic if the symbol can't be found. 4169645SAndreas.Sandberg@ARM.com * 4179645SAndreas.Sandberg@ARM.com * @param symtab Symbol table to use for look up. 4189645SAndreas.Sandberg@ARM.com * @param lbl Function to hook the event to. 4199645SAndreas.Sandberg@ARM.com * @param desc Description to be passed to the event. 4209645SAndreas.Sandberg@ARM.com * @param args Arguments to be forwarded to the event constructor. 4211885SN/A */ 4229645SAndreas.Sandberg@ARM.com template <class T, typename... Args> 4239645SAndreas.Sandberg@ARM.com T *addFuncEvent(const SymbolTable *symtab, const char *lbl, 4249645SAndreas.Sandberg@ARM.com const std::string &desc, Args... args) 4251885SN/A { 4269855Sandreas.hansson@arm.com Addr addr M5_VAR_USED = 0; // initialize only to avoid compiler warning 4271885SN/A 4289850Sandreas.hansson@arm.com#if THE_ISA != NULL_ISA 4291885SN/A if (symtab->findAddress(lbl, addr)) { 4309645SAndreas.Sandberg@ARM.com T *ev = new T(&pcEventQueue, desc, fixFuncEventAddr(addr), 4319645SAndreas.Sandberg@ARM.com std::forward<Args>(args)...); 4321885SN/A return ev; 4331885SN/A } 4349850Sandreas.hansson@arm.com#endif 4351885SN/A 4361885SN/A return NULL; 4371885SN/A } 4381885SN/A 4391885SN/A template <class T> 4409645SAndreas.Sandberg@ARM.com T *addFuncEvent(const SymbolTable *symtab, const char *lbl) 4411885SN/A { 4429645SAndreas.Sandberg@ARM.com return addFuncEvent<T>(symtab, lbl, lbl); 4431885SN/A } 4441885SN/A 4459645SAndreas.Sandberg@ARM.com template <class T, typename... Args> 4469645SAndreas.Sandberg@ARM.com T *addFuncEventOrPanic(const SymbolTable *symtab, const char *lbl, 4479645SAndreas.Sandberg@ARM.com Args... args) 4489645SAndreas.Sandberg@ARM.com { 4499645SAndreas.Sandberg@ARM.com T *e(addFuncEvent<T>(symtab, lbl, std::forward<Args>(args)...)); 4509645SAndreas.Sandberg@ARM.com if (!e) 4519645SAndreas.Sandberg@ARM.com panic("Failed to find symbol '%s'", lbl); 4529645SAndreas.Sandberg@ARM.com return e; 4539645SAndreas.Sandberg@ARM.com } 4549645SAndreas.Sandberg@ARM.com /** @} */ 4559645SAndreas.Sandberg@ARM.com 4569645SAndreas.Sandberg@ARM.com /** @{ */ 4579645SAndreas.Sandberg@ARM.com /** 4589645SAndreas.Sandberg@ARM.com * Add a function-based event to a kernel symbol. 4599645SAndreas.Sandberg@ARM.com * 4609645SAndreas.Sandberg@ARM.com * These functions work like their addFuncEvent() and 4619645SAndreas.Sandberg@ARM.com * addFuncEventOrPanic() counterparts. The only difference is that 4629645SAndreas.Sandberg@ARM.com * they automatically use the kernel symbol table. All arguments 4639645SAndreas.Sandberg@ARM.com * are forwarded to the underlying method. 4649645SAndreas.Sandberg@ARM.com * 4659645SAndreas.Sandberg@ARM.com * @see addFuncEvent() 4669645SAndreas.Sandberg@ARM.com * @see addFuncEventOrPanic() 4679645SAndreas.Sandberg@ARM.com * 4689645SAndreas.Sandberg@ARM.com * @param lbl Function to hook the event to. 4699645SAndreas.Sandberg@ARM.com * @param args Arguments to be passed to addFuncEvent 4709645SAndreas.Sandberg@ARM.com */ 4719645SAndreas.Sandberg@ARM.com template <class T, typename... Args> 4729645SAndreas.Sandberg@ARM.com T *addKernelFuncEvent(const char *lbl, Args... args) 4739645SAndreas.Sandberg@ARM.com { 4749645SAndreas.Sandberg@ARM.com return addFuncEvent<T>(kernelSymtab, lbl, 4759645SAndreas.Sandberg@ARM.com std::forward<Args>(args)...); 4769645SAndreas.Sandberg@ARM.com } 4779645SAndreas.Sandberg@ARM.com 4789645SAndreas.Sandberg@ARM.com template <class T, typename... Args> 4799645SAndreas.Sandberg@ARM.com T *addKernelFuncEventOrPanic(const char *lbl, Args... args) 4809645SAndreas.Sandberg@ARM.com { 4819645SAndreas.Sandberg@ARM.com T *e(addFuncEvent<T>(kernelSymtab, lbl, 4829645SAndreas.Sandberg@ARM.com std::forward<Args>(args)...)); 4839645SAndreas.Sandberg@ARM.com if (!e) 4849645SAndreas.Sandberg@ARM.com panic("Failed to find kernel symbol '%s'", lbl); 4859645SAndreas.Sandberg@ARM.com return e; 4869645SAndreas.Sandberg@ARM.com } 4879645SAndreas.Sandberg@ARM.com /** @} */ 4889645SAndreas.Sandberg@ARM.com 48977SN/A public: 4906658Snate@binkert.org std::vector<BaseRemoteGDB *> remoteGDB; 4911070SN/A std::vector<GDBListener *> gdbListen; 4923960Sgblack@eecs.umich.edu bool breakpoint(); 4931070SN/A 4941070SN/A public: 4954762Snate@binkert.org typedef SystemParams Params; 4961070SN/A 4972158SN/A protected: 4982158SN/A Params *_params; 4991070SN/A 5002158SN/A public: 5011070SN/A System(Params *p); 5022SN/A ~System(); 5032SN/A 50411169Sandreas.hansson@arm.com void initState() override; 5051129SN/A 5062158SN/A const Params *params() const { return (const Params *)_params; } 5072158SN/A 5081070SN/A public: 5092378SN/A 5101070SN/A /** 51111838SCurtis.Dunham@arm.com * Returns the address the kernel starts at. 5121070SN/A * @return address the kernel starts at 5131070SN/A */ 5141070SN/A Addr getKernelStart() const { return kernelStart; } 5151070SN/A 5161070SN/A /** 51711838SCurtis.Dunham@arm.com * Returns the address the kernel ends at. 5181070SN/A * @return address the kernel ends at 5191070SN/A */ 5201070SN/A Addr getKernelEnd() const { return kernelEnd; } 5211070SN/A 5221070SN/A /** 52311838SCurtis.Dunham@arm.com * Returns the address the entry point to the kernel code. 5241070SN/A * @return entry point of the kernel code 5251070SN/A */ 5261070SN/A Addr getKernelEntry() const { return kernelEntry; } 5271070SN/A 5288601Ssteve.reinhardt@amd.com /// Allocate npages contiguous unused physical pages 5298601Ssteve.reinhardt@amd.com /// @return Starting address of first page 5308601Ssteve.reinhardt@amd.com Addr allocPhysPages(int npages); 5312378SN/A 53211005Sandreas.sandberg@arm.com ContextID registerThreadContext(ThreadContext *tc, 53311005Sandreas.sandberg@arm.com ContextID assigned = InvalidContextID); 53411005Sandreas.sandberg@arm.com void replaceThreadContext(ThreadContext *tc, ContextID context_id); 5351070SN/A 53611168Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 53711168Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 5389342SAndreas.Sandberg@arm.com 53911168Sandreas.hansson@arm.com void drainResume() override; 5402SN/A 54177SN/A public: 5427897Shestness@cs.utexas.edu Counter totalNumInsts; 5437897Shestness@cs.utexas.edu EventQueue instEventQueue; 5448666SPrakash.Ramrakhyani@arm.com std::map<std::pair<uint32_t,uint32_t>, Tick> lastWorkItemStarted; 5458666SPrakash.Ramrakhyani@arm.com std::map<uint32_t, Stats::Histogram*> workItemStats; 5467897Shestness@cs.utexas.edu 5472SN/A //////////////////////////////////////////// 5482SN/A // 5492SN/A // STATIC GLOBAL SYSTEM LIST 5502SN/A // 5512SN/A //////////////////////////////////////////// 5522SN/A 5532SN/A static std::vector<System *> systemList; 5542SN/A static int numSystemsRunning; 5552SN/A 5562SN/A static void printSystems(); 5572158SN/A 55811911SBrandon.Potter@amd.com FutexMap futexMap; 5599112Smarc.orr@gmail.com 56011885Sbrandon.potter@amd.com static const int maxPID = 32768; 56111885Sbrandon.potter@amd.com 56211885Sbrandon.potter@amd.com /** Process set to track which PIDs have already been allocated */ 56311885Sbrandon.potter@amd.com std::set<int> PIDs; 56411885Sbrandon.potter@amd.com 56511909SBrandon.Potter@amd.com // By convention, all signals are owned by the receiving process. The 56611909SBrandon.Potter@amd.com // receiver will delete the signal upon reception. 56711909SBrandon.Potter@amd.com std::list<BasicSignal> signalList; 56811909SBrandon.Potter@amd.com 5699292Sandreas.hansson@arm.com protected: 5709292Sandreas.hansson@arm.com 5719292Sandreas.hansson@arm.com /** 5729292Sandreas.hansson@arm.com * If needed, serialize additional symbol table entries for a 57311838SCurtis.Dunham@arm.com * specific subclass of this system. Currently this is used by 5749292Sandreas.hansson@arm.com * Alpha and MIPS. 5759292Sandreas.hansson@arm.com * 5769292Sandreas.hansson@arm.com * @param os stream to serialize to 5779292Sandreas.hansson@arm.com */ 57810905Sandreas.sandberg@arm.com virtual void serializeSymtab(CheckpointOut &os) const {} 5799292Sandreas.hansson@arm.com 5809292Sandreas.hansson@arm.com /** 5819292Sandreas.hansson@arm.com * If needed, unserialize additional symbol table entries for a 5829292Sandreas.hansson@arm.com * specific subclass of this system. 5839292Sandreas.hansson@arm.com * 5849292Sandreas.hansson@arm.com * @param cp checkpoint to unserialize from 5859292Sandreas.hansson@arm.com * @param section relevant section in the checkpoint 5869292Sandreas.hansson@arm.com */ 58710905Sandreas.sandberg@arm.com virtual void unserializeSymtab(CheckpointIn &cp) {} 5882158SN/A 5892SN/A}; 5902SN/A 5919554Sandreas.hansson@arm.comvoid printSystems(); 5929554Sandreas.hansson@arm.com 5932SN/A#endif // __SYSTEM_HH__ 594