system.hh revision 11909
12SN/A/* 210466Sandreas.hansson@arm.com * Copyright (c) 2012, 2014 ARM Limited 38703Sandreas.hansson@arm.com * All rights reserved 48703Sandreas.hansson@arm.com * 58703Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68703Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78703Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88703Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98703Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108703Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118703Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128703Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138703Sandreas.hansson@arm.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422665Ssaidi@eecs.umich.edu * Lisa Hsu 432665Ssaidi@eecs.umich.edu * Nathan Binkert 447897Shestness@cs.utexas.edu * Rick Strong 452SN/A */ 462SN/A 472SN/A#ifndef __SYSTEM_HH__ 482SN/A#define __SYSTEM_HH__ 492SN/A 502SN/A#include <string> 519645SAndreas.Sandberg@ARM.com#include <utility> 5275SN/A#include <vector> 532SN/A 5410466Sandreas.hansson@arm.com#include "arch/isa_traits.hh" 552439SN/A#include "base/loader/symtab.hh" 56603SN/A#include "base/statistics.hh" 5710466Sandreas.hansson@arm.com#include "config/the_isa.hh" 584762Snate@binkert.org#include "enums/MemoryMode.hh" 598703Sandreas.hansson@arm.com#include "mem/mem_object.hh" 602520SN/A#include "mem/port.hh" 619847Sandreas.hansson@arm.com#include "mem/port_proxy.hh" 628931Sandreas.hansson@arm.com#include "mem/physical.hh" 634762Snate@binkert.org#include "params/System.hh" 6411909SBrandon.Potter@amd.com#include "sim/se_signal.hh" 656658Snate@binkert.org 6610494Sandreas.hansson@arm.com/** 6710494Sandreas.hansson@arm.com * To avoid linking errors with LTO, only include the header if we 6810494Sandreas.hansson@arm.com * actually have the definition. 6910494Sandreas.hansson@arm.com */ 7010494Sandreas.hansson@arm.com#if THE_ISA != NULL_ISA 7110494Sandreas.hansson@arm.com#include "cpu/pc_event.hh" 7210494Sandreas.hansson@arm.com#endif 7310494Sandreas.hansson@arm.com 748769Sgblack@eecs.umich.educlass BaseRemoteGDB; 758769Sgblack@eecs.umich.educlass GDBListener; 7611839SCurtis.Dunham@arm.comclass KvmVM; 771634SN/Aclass ObjectFile; 788769Sgblack@eecs.umich.educlass ThreadContext; 792SN/A 808703Sandreas.hansson@arm.comclass System : public MemObject 812SN/A{ 828703Sandreas.hansson@arm.com private: 838703Sandreas.hansson@arm.com 848703Sandreas.hansson@arm.com /** 858703Sandreas.hansson@arm.com * Private class for the system port which is only used as a 868703Sandreas.hansson@arm.com * master for debug access and for non-structural entities that do 878703Sandreas.hansson@arm.com * not have a port of their own. 888703Sandreas.hansson@arm.com */ 898922Swilliam.wang@arm.com class SystemPort : public MasterPort 908703Sandreas.hansson@arm.com { 918703Sandreas.hansson@arm.com public: 928703Sandreas.hansson@arm.com 938703Sandreas.hansson@arm.com /** 948703Sandreas.hansson@arm.com * Create a system port with a name and an owner. 958703Sandreas.hansson@arm.com */ 968703Sandreas.hansson@arm.com SystemPort(const std::string &_name, MemObject *_owner) 978922Swilliam.wang@arm.com : MasterPort(_name, _owner) 988703Sandreas.hansson@arm.com { } 9911169Sandreas.hansson@arm.com bool recvTimingResp(PacketPtr pkt) override 1008703Sandreas.hansson@arm.com { panic("SystemPort does not receive timing!\n"); return false; } 10111169Sandreas.hansson@arm.com void recvReqRetry() override 1028922Swilliam.wang@arm.com { panic("SystemPort does not expect retry!\n"); } 1038703Sandreas.hansson@arm.com }; 1048703Sandreas.hansson@arm.com 1058703Sandreas.hansson@arm.com SystemPort _systemPort; 1068703Sandreas.hansson@arm.com 107603SN/A public: 1082901Ssaidi@eecs.umich.edu 1098703Sandreas.hansson@arm.com /** 1108706Sandreas.hansson@arm.com * After all objects have been created and all ports are 1118706Sandreas.hansson@arm.com * connected, check that the system port is connected. 1128706Sandreas.hansson@arm.com */ 11311169Sandreas.hansson@arm.com void init() override; 1148706Sandreas.hansson@arm.com 1158706Sandreas.hansson@arm.com /** 1168852Sandreas.hansson@arm.com * Get a reference to the system port that can be used by 1178703Sandreas.hansson@arm.com * non-structural simulation objects like processes or threads, or 1188703Sandreas.hansson@arm.com * external entities like loaders and debuggers, etc, to access 1198703Sandreas.hansson@arm.com * the memory system. 1208703Sandreas.hansson@arm.com * 1218852Sandreas.hansson@arm.com * @return a reference to the system port we own 1228703Sandreas.hansson@arm.com */ 1238922Swilliam.wang@arm.com MasterPort& getSystemPort() { return _systemPort; } 1248703Sandreas.hansson@arm.com 1258703Sandreas.hansson@arm.com /** 1268703Sandreas.hansson@arm.com * Additional function to return the Port of a memory object. 1278703Sandreas.hansson@arm.com */ 1289294Sandreas.hansson@arm.com BaseMasterPort& getMasterPort(const std::string &if_name, 12911169Sandreas.hansson@arm.com PortID idx = InvalidPortID) override; 1308703Sandreas.hansson@arm.com 1319524SAndreas.Sandberg@ARM.com /** @{ */ 1329524SAndreas.Sandberg@ARM.com /** 1339524SAndreas.Sandberg@ARM.com * Is the system in atomic mode? 1349524SAndreas.Sandberg@ARM.com * 1359524SAndreas.Sandberg@ARM.com * There are currently two different atomic memory modes: 1369524SAndreas.Sandberg@ARM.com * 'atomic', which supports caches; and 'atomic_noncaching', which 1379524SAndreas.Sandberg@ARM.com * bypasses caches. The latter is used by hardware virtualized 1389524SAndreas.Sandberg@ARM.com * CPUs. SimObjects are expected to use Port::sendAtomic() and 1399524SAndreas.Sandberg@ARM.com * Port::recvAtomic() when accessing memory in this mode. 1409524SAndreas.Sandberg@ARM.com */ 1419524SAndreas.Sandberg@ARM.com bool isAtomicMode() const { 1429524SAndreas.Sandberg@ARM.com return memoryMode == Enums::atomic || 1439524SAndreas.Sandberg@ARM.com memoryMode == Enums::atomic_noncaching; 1444762Snate@binkert.org } 1452901Ssaidi@eecs.umich.edu 1469524SAndreas.Sandberg@ARM.com /** 1479524SAndreas.Sandberg@ARM.com * Is the system in timing mode? 1489524SAndreas.Sandberg@ARM.com * 1499524SAndreas.Sandberg@ARM.com * SimObjects are expected to use Port::sendTiming() and 1509524SAndreas.Sandberg@ARM.com * Port::recvTiming() when accessing memory in this mode. 1519524SAndreas.Sandberg@ARM.com */ 1529524SAndreas.Sandberg@ARM.com bool isTimingMode() const { 1539524SAndreas.Sandberg@ARM.com return memoryMode == Enums::timing; 1549524SAndreas.Sandberg@ARM.com } 1559524SAndreas.Sandberg@ARM.com 1569524SAndreas.Sandberg@ARM.com /** 1579524SAndreas.Sandberg@ARM.com * Should caches be bypassed? 1589524SAndreas.Sandberg@ARM.com * 1599524SAndreas.Sandberg@ARM.com * Some CPUs need to bypass caches to allow direct memory 1609524SAndreas.Sandberg@ARM.com * accesses, which is required for hardware virtualization. 1619524SAndreas.Sandberg@ARM.com */ 1629524SAndreas.Sandberg@ARM.com bool bypassCaches() const { 1639524SAndreas.Sandberg@ARM.com return memoryMode == Enums::atomic_noncaching; 1649524SAndreas.Sandberg@ARM.com } 1659524SAndreas.Sandberg@ARM.com /** @} */ 1669524SAndreas.Sandberg@ARM.com 1679524SAndreas.Sandberg@ARM.com /** @{ */ 1689524SAndreas.Sandberg@ARM.com /** 1699524SAndreas.Sandberg@ARM.com * Get the memory mode of the system. 1709524SAndreas.Sandberg@ARM.com * 1719524SAndreas.Sandberg@ARM.com * \warn This should only be used by the Python world. The C++ 1729524SAndreas.Sandberg@ARM.com * world should use one of the query functions above 1739524SAndreas.Sandberg@ARM.com * (isAtomicMode(), isTimingMode(), bypassCaches()). 1749524SAndreas.Sandberg@ARM.com */ 1759524SAndreas.Sandberg@ARM.com Enums::MemoryMode getMemoryMode() const { return memoryMode; } 1769524SAndreas.Sandberg@ARM.com 1779524SAndreas.Sandberg@ARM.com /** 1789524SAndreas.Sandberg@ARM.com * Change the memory mode of the system. 1799524SAndreas.Sandberg@ARM.com * 1809524SAndreas.Sandberg@ARM.com * \warn This should only be called by the Python! 1819524SAndreas.Sandberg@ARM.com * 1829524SAndreas.Sandberg@ARM.com * @param mode Mode to change to (atomic/timing/...) 1832901Ssaidi@eecs.umich.edu */ 1844762Snate@binkert.org void setMemoryMode(Enums::MemoryMode mode); 1859524SAndreas.Sandberg@ARM.com /** @} */ 1862901Ssaidi@eecs.umich.edu 1879814Sandreas.hansson@arm.com /** 1889814Sandreas.hansson@arm.com * Get the cache line size of the system. 1899814Sandreas.hansson@arm.com */ 1909814Sandreas.hansson@arm.com unsigned int cacheLineSize() const { return _cacheLineSize; } 1919814Sandreas.hansson@arm.com 1929850Sandreas.hansson@arm.com#if THE_ISA != NULL_ISA 1932SN/A PCEventQueue pcEventQueue; 1949850Sandreas.hansson@arm.com#endif 1952SN/A 1962680Sktlim@umich.edu std::vector<ThreadContext *> threadContexts; 1975714Shsul@eecs.umich.edu int _numContexts; 19811146Smitch.hayenga@arm.com const bool multiThread; 1991806SN/A 20011005Sandreas.sandberg@arm.com ThreadContext *getThreadContext(ContextID tid) 2015713Shsul@eecs.umich.edu { 2025713Shsul@eecs.umich.edu return threadContexts[tid]; 2035713Shsul@eecs.umich.edu } 2045713Shsul@eecs.umich.edu 2055714Shsul@eecs.umich.edu int numContexts() 2061806SN/A { 2076227Snate@binkert.org assert(_numContexts == (int)threadContexts.size()); 2085714Shsul@eecs.umich.edu return _numContexts; 2091806SN/A } 210180SN/A 2116029Ssteve.reinhardt@amd.com /** Return number of running (non-halted) thread contexts in 2126029Ssteve.reinhardt@amd.com * system. These threads could be Active or Suspended. */ 2136029Ssteve.reinhardt@amd.com int numRunningContexts(); 2146029Ssteve.reinhardt@amd.com 2158765Sgblack@eecs.umich.edu Addr pagePtr; 2168765Sgblack@eecs.umich.edu 2172378SN/A uint64_t init_param; 2182378SN/A 2192520SN/A /** Port to physical memory used for writing object files into ram at 2202520SN/A * boot.*/ 2218852Sandreas.hansson@arm.com PortProxy physProxy; 2222520SN/A 2231885SN/A /** kernel symbol table */ 2241070SN/A SymbolTable *kernelSymtab; 225954SN/A 2261070SN/A /** Object pointer for the kernel code */ 2271070SN/A ObjectFile *kernel; 2281070SN/A 22911838SCurtis.Dunham@arm.com /** Beginning of kernel code */ 2301070SN/A Addr kernelStart; 2311070SN/A 2321070SN/A /** End of kernel code */ 2331070SN/A Addr kernelEnd; 2341070SN/A 2351070SN/A /** Entry point in the kernel to start at */ 2361070SN/A Addr kernelEntry; 2371070SN/A 2387580SAli.Saidi@arm.com /** Mask that should be anded for binary/symbol loading. 2397580SAli.Saidi@arm.com * This allows one two different OS requirements for the same ISA to be 2407580SAli.Saidi@arm.com * handled. Some OSes are compiled for a virtual address and need to be 2417580SAli.Saidi@arm.com * loaded into physical memory that starts at address 0, while other 2427580SAli.Saidi@arm.com * bare metal tools generate images that start at address 0. 2437580SAli.Saidi@arm.com */ 2447580SAli.Saidi@arm.com Addr loadAddrMask; 2457580SAli.Saidi@arm.com 24610037SARM gem5 Developers /** Offset that should be used for binary/symbol loading. 24711838SCurtis.Dunham@arm.com * This further allows more flexibility than the loadAddrMask allows alone 24811838SCurtis.Dunham@arm.com * in loading kernels and similar. The loadAddrOffset is applied after the 24910037SARM gem5 Developers * loadAddrMask. 25010037SARM gem5 Developers */ 25110037SARM gem5 Developers Addr loadAddrOffset; 25210037SARM gem5 Developers 2534997Sgblack@eecs.umich.edu public: 25411839SCurtis.Dunham@arm.com /** 25511839SCurtis.Dunham@arm.com * Get a pointer to the Kernel Virtual Machine (KVM) SimObject, 25611839SCurtis.Dunham@arm.com * if present. 25711839SCurtis.Dunham@arm.com */ 25811839SCurtis.Dunham@arm.com KvmVM* getKvmVM() { 25911839SCurtis.Dunham@arm.com return kvmVM; 26011839SCurtis.Dunham@arm.com } 26111839SCurtis.Dunham@arm.com 2628931Sandreas.hansson@arm.com /** Get a pointer to access the physical memory of the system */ 2638931Sandreas.hansson@arm.com PhysicalMemory& getPhysMem() { return physmem; } 2648931Sandreas.hansson@arm.com 2655795Ssaidi@eecs.umich.edu /** Amount of physical memory that is still free */ 2668931Sandreas.hansson@arm.com Addr freeMemSize() const; 2675795Ssaidi@eecs.umich.edu 2685795Ssaidi@eecs.umich.edu /** Amount of physical memory that exists */ 2698931Sandreas.hansson@arm.com Addr memSize() const; 2708931Sandreas.hansson@arm.com 2718931Sandreas.hansson@arm.com /** 2728931Sandreas.hansson@arm.com * Check if a physical address is within a range of a memory that 2738931Sandreas.hansson@arm.com * is part of the global address map. 2748931Sandreas.hansson@arm.com * 2758931Sandreas.hansson@arm.com * @param addr A physical address 2768931Sandreas.hansson@arm.com * @return Whether the address corresponds to a memory 2778931Sandreas.hansson@arm.com */ 2788931Sandreas.hansson@arm.com bool isMemAddr(Addr addr) const; 2795795Ssaidi@eecs.umich.edu 28010467Sandreas.hansson@arm.com /** 28110467Sandreas.hansson@arm.com * Get the architecture. 28210467Sandreas.hansson@arm.com */ 28310467Sandreas.hansson@arm.com Arch getArch() const { return Arch::TheISA; } 28410467Sandreas.hansson@arm.com 28510466Sandreas.hansson@arm.com /** 28610466Sandreas.hansson@arm.com * Get the page bytes for the ISA. 28710466Sandreas.hansson@arm.com */ 28810466Sandreas.hansson@arm.com Addr getPageBytes() const { return TheISA::PageBytes; } 28910466Sandreas.hansson@arm.com 29010466Sandreas.hansson@arm.com /** 29111838SCurtis.Dunham@arm.com * Get the number of bits worth of in-page address for the ISA. 29210466Sandreas.hansson@arm.com */ 29310466Sandreas.hansson@arm.com Addr getPageShift() const { return TheISA::PageShift; } 29410466Sandreas.hansson@arm.com 29511420Sdavid.guillen@arm.com /** 29611420Sdavid.guillen@arm.com * The thermal model used for this system (if any). 29711420Sdavid.guillen@arm.com */ 29811420Sdavid.guillen@arm.com ThermalModel * getThermalModel() const { return thermalModel; } 29911420Sdavid.guillen@arm.com 3001885SN/A protected: 3018931Sandreas.hansson@arm.com 30211839SCurtis.Dunham@arm.com KvmVM *const kvmVM; 30311839SCurtis.Dunham@arm.com 3048931Sandreas.hansson@arm.com PhysicalMemory physmem; 3058931Sandreas.hansson@arm.com 3064762Snate@binkert.org Enums::MemoryMode memoryMode; 3079814Sandreas.hansson@arm.com 3089814Sandreas.hansson@arm.com const unsigned int _cacheLineSize; 3099814Sandreas.hansson@arm.com 3107914SBrad.Beckmann@amd.com uint64_t workItemsBegin; 3117914SBrad.Beckmann@amd.com uint64_t workItemsEnd; 3128666SPrakash.Ramrakhyani@arm.com uint32_t numWorkIds; 3137914SBrad.Beckmann@amd.com std::vector<bool> activeCpus; 3147914SBrad.Beckmann@amd.com 31511838SCurtis.Dunham@arm.com /** This array is a per-system list of all devices capable of issuing a 3168832SAli.Saidi@ARM.com * memory system request and an associated string for each master id. 3178832SAli.Saidi@ARM.com * It's used to uniquely id any master in the system by name for things 3188832SAli.Saidi@ARM.com * like cache statistics. 3198832SAli.Saidi@ARM.com */ 3208832SAli.Saidi@ARM.com std::vector<std::string> masterIds; 3218832SAli.Saidi@ARM.com 32211420Sdavid.guillen@arm.com ThermalModel * thermalModel; 32311420Sdavid.guillen@arm.com 3247914SBrad.Beckmann@amd.com public: 3258832SAli.Saidi@ARM.com 3268832SAli.Saidi@ARM.com /** Request an id used to create a request object in the system. All objects 3278832SAli.Saidi@ARM.com * that intend to issues requests into the memory system must request an id 3288832SAli.Saidi@ARM.com * in the init() phase of startup. All master ids must be fixed by the 32911838SCurtis.Dunham@arm.com * regStats() phase that immediately precedes it. This allows objects in 33011838SCurtis.Dunham@arm.com * the memory system to understand how many masters may exist and 3318832SAli.Saidi@ARM.com * appropriately name the bins of their per-master stats before the stats 3328832SAli.Saidi@ARM.com * are finalized 3338832SAli.Saidi@ARM.com */ 3348832SAli.Saidi@ARM.com MasterID getMasterId(std::string req_name); 3358832SAli.Saidi@ARM.com 3368832SAli.Saidi@ARM.com /** Get the name of an object for a given request id. 3378832SAli.Saidi@ARM.com */ 3388832SAli.Saidi@ARM.com std::string getMasterName(MasterID master_id); 3398832SAli.Saidi@ARM.com 3408832SAli.Saidi@ARM.com /** Get the number of masters registered in the system */ 3418832SAli.Saidi@ARM.com MasterID maxMasters() 3428832SAli.Saidi@ARM.com { 3438832SAli.Saidi@ARM.com return masterIds.size(); 3448832SAli.Saidi@ARM.com } 3458832SAli.Saidi@ARM.com 34611169Sandreas.hansson@arm.com void regStats() override; 3477914SBrad.Beckmann@amd.com /** 3487914SBrad.Beckmann@amd.com * Called by pseudo_inst to track the number of work items started by this 3497914SBrad.Beckmann@amd.com * system. 3507914SBrad.Beckmann@amd.com */ 3518666SPrakash.Ramrakhyani@arm.com uint64_t 3527914SBrad.Beckmann@amd.com incWorkItemsBegin() 3537914SBrad.Beckmann@amd.com { 3547914SBrad.Beckmann@amd.com return ++workItemsBegin; 3557914SBrad.Beckmann@amd.com } 3567914SBrad.Beckmann@amd.com 3577914SBrad.Beckmann@amd.com /** 3587914SBrad.Beckmann@amd.com * Called by pseudo_inst to track the number of work items completed by 3597914SBrad.Beckmann@amd.com * this system. 3607914SBrad.Beckmann@amd.com */ 36110037SARM gem5 Developers uint64_t 3627914SBrad.Beckmann@amd.com incWorkItemsEnd() 3637914SBrad.Beckmann@amd.com { 3647914SBrad.Beckmann@amd.com return ++workItemsEnd; 3657914SBrad.Beckmann@amd.com } 3667914SBrad.Beckmann@amd.com 3677914SBrad.Beckmann@amd.com /** 3687914SBrad.Beckmann@amd.com * Called by pseudo_inst to mark the cpus actively executing work items. 3697914SBrad.Beckmann@amd.com * Returns the total number of cpus that have executed work item begin or 3707914SBrad.Beckmann@amd.com * ends. 3717914SBrad.Beckmann@amd.com */ 37210037SARM gem5 Developers int 3737914SBrad.Beckmann@amd.com markWorkItem(int index) 3747914SBrad.Beckmann@amd.com { 3757914SBrad.Beckmann@amd.com int count = 0; 3767914SBrad.Beckmann@amd.com assert(index < activeCpus.size()); 3777914SBrad.Beckmann@amd.com activeCpus[index] = true; 37810037SARM gem5 Developers for (std::vector<bool>::iterator i = activeCpus.begin(); 3797914SBrad.Beckmann@amd.com i < activeCpus.end(); i++) { 3807914SBrad.Beckmann@amd.com if (*i) count++; 3817914SBrad.Beckmann@amd.com } 3827914SBrad.Beckmann@amd.com return count; 3837914SBrad.Beckmann@amd.com } 3842901Ssaidi@eecs.umich.edu 3858666SPrakash.Ramrakhyani@arm.com inline void workItemBegin(uint32_t tid, uint32_t workid) 3868666SPrakash.Ramrakhyani@arm.com { 3878666SPrakash.Ramrakhyani@arm.com std::pair<uint32_t,uint32_t> p(tid, workid); 3888666SPrakash.Ramrakhyani@arm.com lastWorkItemStarted[p] = curTick(); 3898666SPrakash.Ramrakhyani@arm.com } 3908666SPrakash.Ramrakhyani@arm.com 3918666SPrakash.Ramrakhyani@arm.com void workItemEnd(uint32_t tid, uint32_t workid); 3928666SPrakash.Ramrakhyani@arm.com 3931885SN/A /** 3941885SN/A * Fix up an address used to match PCs for hooking simulator 3951885SN/A * events on to target function executions. See comment in 3961885SN/A * system.cc for details. 3971885SN/A */ 3988769Sgblack@eecs.umich.edu virtual Addr fixFuncEventAddr(Addr addr) 3998769Sgblack@eecs.umich.edu { 4008769Sgblack@eecs.umich.edu panic("Base fixFuncEventAddr not implemented.\n"); 4018769Sgblack@eecs.umich.edu } 4021885SN/A 4039645SAndreas.Sandberg@ARM.com /** @{ */ 4041885SN/A /** 4051885SN/A * Add a function-based event to the given function, to be looked 4061885SN/A * up in the specified symbol table. 4079645SAndreas.Sandberg@ARM.com * 4089645SAndreas.Sandberg@ARM.com * The ...OrPanic flavor of the method causes the simulator to 4099645SAndreas.Sandberg@ARM.com * panic if the symbol can't be found. 4109645SAndreas.Sandberg@ARM.com * 4119645SAndreas.Sandberg@ARM.com * @param symtab Symbol table to use for look up. 4129645SAndreas.Sandberg@ARM.com * @param lbl Function to hook the event to. 4139645SAndreas.Sandberg@ARM.com * @param desc Description to be passed to the event. 4149645SAndreas.Sandberg@ARM.com * @param args Arguments to be forwarded to the event constructor. 4151885SN/A */ 4169645SAndreas.Sandberg@ARM.com template <class T, typename... Args> 4179645SAndreas.Sandberg@ARM.com T *addFuncEvent(const SymbolTable *symtab, const char *lbl, 4189645SAndreas.Sandberg@ARM.com const std::string &desc, Args... args) 4191885SN/A { 4209855Sandreas.hansson@arm.com Addr addr M5_VAR_USED = 0; // initialize only to avoid compiler warning 4211885SN/A 4229850Sandreas.hansson@arm.com#if THE_ISA != NULL_ISA 4231885SN/A if (symtab->findAddress(lbl, addr)) { 4249645SAndreas.Sandberg@ARM.com T *ev = new T(&pcEventQueue, desc, fixFuncEventAddr(addr), 4259645SAndreas.Sandberg@ARM.com std::forward<Args>(args)...); 4261885SN/A return ev; 4271885SN/A } 4289850Sandreas.hansson@arm.com#endif 4291885SN/A 4301885SN/A return NULL; 4311885SN/A } 4321885SN/A 4331885SN/A template <class T> 4349645SAndreas.Sandberg@ARM.com T *addFuncEvent(const SymbolTable *symtab, const char *lbl) 4351885SN/A { 4369645SAndreas.Sandberg@ARM.com return addFuncEvent<T>(symtab, lbl, lbl); 4371885SN/A } 4381885SN/A 4399645SAndreas.Sandberg@ARM.com template <class T, typename... Args> 4409645SAndreas.Sandberg@ARM.com T *addFuncEventOrPanic(const SymbolTable *symtab, const char *lbl, 4419645SAndreas.Sandberg@ARM.com Args... args) 4429645SAndreas.Sandberg@ARM.com { 4439645SAndreas.Sandberg@ARM.com T *e(addFuncEvent<T>(symtab, lbl, std::forward<Args>(args)...)); 4449645SAndreas.Sandberg@ARM.com if (!e) 4459645SAndreas.Sandberg@ARM.com panic("Failed to find symbol '%s'", lbl); 4469645SAndreas.Sandberg@ARM.com return e; 4479645SAndreas.Sandberg@ARM.com } 4489645SAndreas.Sandberg@ARM.com /** @} */ 4499645SAndreas.Sandberg@ARM.com 4509645SAndreas.Sandberg@ARM.com /** @{ */ 4519645SAndreas.Sandberg@ARM.com /** 4529645SAndreas.Sandberg@ARM.com * Add a function-based event to a kernel symbol. 4539645SAndreas.Sandberg@ARM.com * 4549645SAndreas.Sandberg@ARM.com * These functions work like their addFuncEvent() and 4559645SAndreas.Sandberg@ARM.com * addFuncEventOrPanic() counterparts. The only difference is that 4569645SAndreas.Sandberg@ARM.com * they automatically use the kernel symbol table. All arguments 4579645SAndreas.Sandberg@ARM.com * are forwarded to the underlying method. 4589645SAndreas.Sandberg@ARM.com * 4599645SAndreas.Sandberg@ARM.com * @see addFuncEvent() 4609645SAndreas.Sandberg@ARM.com * @see addFuncEventOrPanic() 4619645SAndreas.Sandberg@ARM.com * 4629645SAndreas.Sandberg@ARM.com * @param lbl Function to hook the event to. 4639645SAndreas.Sandberg@ARM.com * @param args Arguments to be passed to addFuncEvent 4649645SAndreas.Sandberg@ARM.com */ 4659645SAndreas.Sandberg@ARM.com template <class T, typename... Args> 4669645SAndreas.Sandberg@ARM.com T *addKernelFuncEvent(const char *lbl, Args... args) 4679645SAndreas.Sandberg@ARM.com { 4689645SAndreas.Sandberg@ARM.com return addFuncEvent<T>(kernelSymtab, lbl, 4699645SAndreas.Sandberg@ARM.com std::forward<Args>(args)...); 4709645SAndreas.Sandberg@ARM.com } 4719645SAndreas.Sandberg@ARM.com 4729645SAndreas.Sandberg@ARM.com template <class T, typename... Args> 4739645SAndreas.Sandberg@ARM.com T *addKernelFuncEventOrPanic(const char *lbl, Args... args) 4749645SAndreas.Sandberg@ARM.com { 4759645SAndreas.Sandberg@ARM.com T *e(addFuncEvent<T>(kernelSymtab, lbl, 4769645SAndreas.Sandberg@ARM.com std::forward<Args>(args)...)); 4779645SAndreas.Sandberg@ARM.com if (!e) 4789645SAndreas.Sandberg@ARM.com panic("Failed to find kernel symbol '%s'", lbl); 4799645SAndreas.Sandberg@ARM.com return e; 4809645SAndreas.Sandberg@ARM.com } 4819645SAndreas.Sandberg@ARM.com /** @} */ 4829645SAndreas.Sandberg@ARM.com 48377SN/A public: 4846658Snate@binkert.org std::vector<BaseRemoteGDB *> remoteGDB; 4851070SN/A std::vector<GDBListener *> gdbListen; 4863960Sgblack@eecs.umich.edu bool breakpoint(); 4871070SN/A 4881070SN/A public: 4894762Snate@binkert.org typedef SystemParams Params; 4901070SN/A 4912158SN/A protected: 4922158SN/A Params *_params; 4931070SN/A 4942158SN/A public: 4951070SN/A System(Params *p); 4962SN/A ~System(); 4972SN/A 49811169Sandreas.hansson@arm.com void initState() override; 4991129SN/A 5002158SN/A const Params *params() const { return (const Params *)_params; } 5012158SN/A 5021070SN/A public: 5032378SN/A 5041070SN/A /** 50511838SCurtis.Dunham@arm.com * Returns the address the kernel starts at. 5061070SN/A * @return address the kernel starts at 5071070SN/A */ 5081070SN/A Addr getKernelStart() const { return kernelStart; } 5091070SN/A 5101070SN/A /** 51111838SCurtis.Dunham@arm.com * Returns the address the kernel ends at. 5121070SN/A * @return address the kernel ends at 5131070SN/A */ 5141070SN/A Addr getKernelEnd() const { return kernelEnd; } 5151070SN/A 5161070SN/A /** 51711838SCurtis.Dunham@arm.com * Returns the address the entry point to the kernel code. 5181070SN/A * @return entry point of the kernel code 5191070SN/A */ 5201070SN/A Addr getKernelEntry() const { return kernelEntry; } 5211070SN/A 5228601Ssteve.reinhardt@amd.com /// Allocate npages contiguous unused physical pages 5238601Ssteve.reinhardt@amd.com /// @return Starting address of first page 5248601Ssteve.reinhardt@amd.com Addr allocPhysPages(int npages); 5252378SN/A 52611005Sandreas.sandberg@arm.com ContextID registerThreadContext(ThreadContext *tc, 52711005Sandreas.sandberg@arm.com ContextID assigned = InvalidContextID); 52811005Sandreas.sandberg@arm.com void replaceThreadContext(ThreadContext *tc, ContextID context_id); 5291070SN/A 53011168Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 53111168Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 5329342SAndreas.Sandberg@arm.com 53311168Sandreas.hansson@arm.com void drainResume() override; 5342SN/A 53577SN/A public: 5367897Shestness@cs.utexas.edu Counter totalNumInsts; 5377897Shestness@cs.utexas.edu EventQueue instEventQueue; 5388666SPrakash.Ramrakhyani@arm.com std::map<std::pair<uint32_t,uint32_t>, Tick> lastWorkItemStarted; 5398666SPrakash.Ramrakhyani@arm.com std::map<uint32_t, Stats::Histogram*> workItemStats; 5407897Shestness@cs.utexas.edu 5412SN/A //////////////////////////////////////////// 5422SN/A // 5432SN/A // STATIC GLOBAL SYSTEM LIST 5442SN/A // 5452SN/A //////////////////////////////////////////// 5462SN/A 5472SN/A static std::vector<System *> systemList; 5482SN/A static int numSystemsRunning; 5492SN/A 5502SN/A static void printSystems(); 5512158SN/A 5529112Smarc.orr@gmail.com // For futex system call 5539112Smarc.orr@gmail.com std::map<uint64_t, std::list<ThreadContext *> * > futexMap; 5549112Smarc.orr@gmail.com 55511885Sbrandon.potter@amd.com static const int maxPID = 32768; 55611885Sbrandon.potter@amd.com 55711885Sbrandon.potter@amd.com /** Process set to track which PIDs have already been allocated */ 55811885Sbrandon.potter@amd.com std::set<int> PIDs; 55911885Sbrandon.potter@amd.com 56011909SBrandon.Potter@amd.com // By convention, all signals are owned by the receiving process. The 56111909SBrandon.Potter@amd.com // receiver will delete the signal upon reception. 56211909SBrandon.Potter@amd.com std::list<BasicSignal> signalList; 56311909SBrandon.Potter@amd.com 5649292Sandreas.hansson@arm.com protected: 5659292Sandreas.hansson@arm.com 5669292Sandreas.hansson@arm.com /** 5679292Sandreas.hansson@arm.com * If needed, serialize additional symbol table entries for a 56811838SCurtis.Dunham@arm.com * specific subclass of this system. Currently this is used by 5699292Sandreas.hansson@arm.com * Alpha and MIPS. 5709292Sandreas.hansson@arm.com * 5719292Sandreas.hansson@arm.com * @param os stream to serialize to 5729292Sandreas.hansson@arm.com */ 57310905Sandreas.sandberg@arm.com virtual void serializeSymtab(CheckpointOut &os) const {} 5749292Sandreas.hansson@arm.com 5759292Sandreas.hansson@arm.com /** 5769292Sandreas.hansson@arm.com * If needed, unserialize additional symbol table entries for a 5779292Sandreas.hansson@arm.com * specific subclass of this system. 5789292Sandreas.hansson@arm.com * 5799292Sandreas.hansson@arm.com * @param cp checkpoint to unserialize from 5809292Sandreas.hansson@arm.com * @param section relevant section in the checkpoint 5819292Sandreas.hansson@arm.com */ 58210905Sandreas.sandberg@arm.com virtual void unserializeSymtab(CheckpointIn &cp) {} 5832158SN/A 5842SN/A}; 5852SN/A 5869554Sandreas.hansson@arm.comvoid printSystems(); 5879554Sandreas.hansson@arm.com 5882SN/A#endif // __SYSTEM_HH__ 589