system.hh revision 11168
12SN/A/* 210466Sandreas.hansson@arm.com * Copyright (c) 2012, 2014 ARM Limited 38703Sandreas.hansson@arm.com * All rights reserved 48703Sandreas.hansson@arm.com * 58703Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68703Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78703Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88703Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98703Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108703Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118703Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128703Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138703Sandreas.hansson@arm.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422665Ssaidi@eecs.umich.edu * Lisa Hsu 432665Ssaidi@eecs.umich.edu * Nathan Binkert 447897Shestness@cs.utexas.edu * Rick Strong 452SN/A */ 462SN/A 472SN/A#ifndef __SYSTEM_HH__ 482SN/A#define __SYSTEM_HH__ 492SN/A 502SN/A#include <string> 519645SAndreas.Sandberg@ARM.com#include <utility> 5275SN/A#include <vector> 532SN/A 5410466Sandreas.hansson@arm.com#include "arch/isa_traits.hh" 552439SN/A#include "base/loader/symtab.hh" 562439SN/A#include "base/misc.hh" 57603SN/A#include "base/statistics.hh" 5810466Sandreas.hansson@arm.com#include "config/the_isa.hh" 594762Snate@binkert.org#include "enums/MemoryMode.hh" 608703Sandreas.hansson@arm.com#include "mem/mem_object.hh" 612520SN/A#include "mem/port.hh" 629847Sandreas.hansson@arm.com#include "mem/port_proxy.hh" 638931Sandreas.hansson@arm.com#include "mem/physical.hh" 644762Snate@binkert.org#include "params/System.hh" 656658Snate@binkert.org 6610494Sandreas.hansson@arm.com/** 6710494Sandreas.hansson@arm.com * To avoid linking errors with LTO, only include the header if we 6810494Sandreas.hansson@arm.com * actually have the definition. 6910494Sandreas.hansson@arm.com */ 7010494Sandreas.hansson@arm.com#if THE_ISA != NULL_ISA 7110494Sandreas.hansson@arm.com#include "cpu/pc_event.hh" 7210494Sandreas.hansson@arm.com#endif 7310494Sandreas.hansson@arm.com 741634SN/Aclass BaseCPU; 758769Sgblack@eecs.umich.educlass BaseRemoteGDB; 768769Sgblack@eecs.umich.educlass GDBListener; 771634SN/Aclass ObjectFile; 78803SN/Aclass Platform; 798769Sgblack@eecs.umich.educlass ThreadContext; 802SN/A 818703Sandreas.hansson@arm.comclass System : public MemObject 822SN/A{ 838703Sandreas.hansson@arm.com private: 848703Sandreas.hansson@arm.com 858703Sandreas.hansson@arm.com /** 868703Sandreas.hansson@arm.com * Private class for the system port which is only used as a 878703Sandreas.hansson@arm.com * master for debug access and for non-structural entities that do 888703Sandreas.hansson@arm.com * not have a port of their own. 898703Sandreas.hansson@arm.com */ 908922Swilliam.wang@arm.com class SystemPort : public MasterPort 918703Sandreas.hansson@arm.com { 928703Sandreas.hansson@arm.com public: 938703Sandreas.hansson@arm.com 948703Sandreas.hansson@arm.com /** 958703Sandreas.hansson@arm.com * Create a system port with a name and an owner. 968703Sandreas.hansson@arm.com */ 978703Sandreas.hansson@arm.com SystemPort(const std::string &_name, MemObject *_owner) 988922Swilliam.wang@arm.com : MasterPort(_name, _owner) 998703Sandreas.hansson@arm.com { } 1008975Sandreas.hansson@arm.com bool recvTimingResp(PacketPtr pkt) 1018703Sandreas.hansson@arm.com { panic("SystemPort does not receive timing!\n"); return false; } 10210713Sandreas.hansson@arm.com void recvReqRetry() 1038922Swilliam.wang@arm.com { panic("SystemPort does not expect retry!\n"); } 1048703Sandreas.hansson@arm.com }; 1058703Sandreas.hansson@arm.com 1068703Sandreas.hansson@arm.com SystemPort _systemPort; 1078703Sandreas.hansson@arm.com 108603SN/A public: 1092901Ssaidi@eecs.umich.edu 1108703Sandreas.hansson@arm.com /** 1118706Sandreas.hansson@arm.com * After all objects have been created and all ports are 1128706Sandreas.hansson@arm.com * connected, check that the system port is connected. 1138706Sandreas.hansson@arm.com */ 1148706Sandreas.hansson@arm.com virtual void init(); 1158706Sandreas.hansson@arm.com 1168706Sandreas.hansson@arm.com /** 1178852Sandreas.hansson@arm.com * Get a reference to the system port that can be used by 1188703Sandreas.hansson@arm.com * non-structural simulation objects like processes or threads, or 1198703Sandreas.hansson@arm.com * external entities like loaders and debuggers, etc, to access 1208703Sandreas.hansson@arm.com * the memory system. 1218703Sandreas.hansson@arm.com * 1228852Sandreas.hansson@arm.com * @return a reference to the system port we own 1238703Sandreas.hansson@arm.com */ 1248922Swilliam.wang@arm.com MasterPort& getSystemPort() { return _systemPort; } 1258703Sandreas.hansson@arm.com 1268703Sandreas.hansson@arm.com /** 1278703Sandreas.hansson@arm.com * Additional function to return the Port of a memory object. 1288703Sandreas.hansson@arm.com */ 1299294Sandreas.hansson@arm.com BaseMasterPort& getMasterPort(const std::string &if_name, 1309294Sandreas.hansson@arm.com PortID idx = InvalidPortID); 1318703Sandreas.hansson@arm.com 1329524SAndreas.Sandberg@ARM.com /** @{ */ 1339524SAndreas.Sandberg@ARM.com /** 1349524SAndreas.Sandberg@ARM.com * Is the system in atomic mode? 1359524SAndreas.Sandberg@ARM.com * 1369524SAndreas.Sandberg@ARM.com * There are currently two different atomic memory modes: 1379524SAndreas.Sandberg@ARM.com * 'atomic', which supports caches; and 'atomic_noncaching', which 1389524SAndreas.Sandberg@ARM.com * bypasses caches. The latter is used by hardware virtualized 1399524SAndreas.Sandberg@ARM.com * CPUs. SimObjects are expected to use Port::sendAtomic() and 1409524SAndreas.Sandberg@ARM.com * Port::recvAtomic() when accessing memory in this mode. 1419524SAndreas.Sandberg@ARM.com */ 1429524SAndreas.Sandberg@ARM.com bool isAtomicMode() const { 1439524SAndreas.Sandberg@ARM.com return memoryMode == Enums::atomic || 1449524SAndreas.Sandberg@ARM.com memoryMode == Enums::atomic_noncaching; 1454762Snate@binkert.org } 1462901Ssaidi@eecs.umich.edu 1479524SAndreas.Sandberg@ARM.com /** 1489524SAndreas.Sandberg@ARM.com * Is the system in timing mode? 1499524SAndreas.Sandberg@ARM.com * 1509524SAndreas.Sandberg@ARM.com * SimObjects are expected to use Port::sendTiming() and 1519524SAndreas.Sandberg@ARM.com * Port::recvTiming() when accessing memory in this mode. 1529524SAndreas.Sandberg@ARM.com */ 1539524SAndreas.Sandberg@ARM.com bool isTimingMode() const { 1549524SAndreas.Sandberg@ARM.com return memoryMode == Enums::timing; 1559524SAndreas.Sandberg@ARM.com } 1569524SAndreas.Sandberg@ARM.com 1579524SAndreas.Sandberg@ARM.com /** 1589524SAndreas.Sandberg@ARM.com * Should caches be bypassed? 1599524SAndreas.Sandberg@ARM.com * 1609524SAndreas.Sandberg@ARM.com * Some CPUs need to bypass caches to allow direct memory 1619524SAndreas.Sandberg@ARM.com * accesses, which is required for hardware virtualization. 1629524SAndreas.Sandberg@ARM.com */ 1639524SAndreas.Sandberg@ARM.com bool bypassCaches() const { 1649524SAndreas.Sandberg@ARM.com return memoryMode == Enums::atomic_noncaching; 1659524SAndreas.Sandberg@ARM.com } 1669524SAndreas.Sandberg@ARM.com /** @} */ 1679524SAndreas.Sandberg@ARM.com 1689524SAndreas.Sandberg@ARM.com /** @{ */ 1699524SAndreas.Sandberg@ARM.com /** 1709524SAndreas.Sandberg@ARM.com * Get the memory mode of the system. 1719524SAndreas.Sandberg@ARM.com * 1729524SAndreas.Sandberg@ARM.com * \warn This should only be used by the Python world. The C++ 1739524SAndreas.Sandberg@ARM.com * world should use one of the query functions above 1749524SAndreas.Sandberg@ARM.com * (isAtomicMode(), isTimingMode(), bypassCaches()). 1759524SAndreas.Sandberg@ARM.com */ 1769524SAndreas.Sandberg@ARM.com Enums::MemoryMode getMemoryMode() const { return memoryMode; } 1779524SAndreas.Sandberg@ARM.com 1789524SAndreas.Sandberg@ARM.com /** 1799524SAndreas.Sandberg@ARM.com * Change the memory mode of the system. 1809524SAndreas.Sandberg@ARM.com * 1819524SAndreas.Sandberg@ARM.com * \warn This should only be called by the Python! 1829524SAndreas.Sandberg@ARM.com * 1839524SAndreas.Sandberg@ARM.com * @param mode Mode to change to (atomic/timing/...) 1842901Ssaidi@eecs.umich.edu */ 1854762Snate@binkert.org void setMemoryMode(Enums::MemoryMode mode); 1869524SAndreas.Sandberg@ARM.com /** @} */ 1872901Ssaidi@eecs.umich.edu 1889814Sandreas.hansson@arm.com /** 1899814Sandreas.hansson@arm.com * Get the cache line size of the system. 1909814Sandreas.hansson@arm.com */ 1919814Sandreas.hansson@arm.com unsigned int cacheLineSize() const { return _cacheLineSize; } 1929814Sandreas.hansson@arm.com 1939850Sandreas.hansson@arm.com#if THE_ISA != NULL_ISA 1942SN/A PCEventQueue pcEventQueue; 1959850Sandreas.hansson@arm.com#endif 1962SN/A 1972680Sktlim@umich.edu std::vector<ThreadContext *> threadContexts; 1985714Shsul@eecs.umich.edu int _numContexts; 19911146Smitch.hayenga@arm.com const bool multiThread; 2001806SN/A 20111005Sandreas.sandberg@arm.com ThreadContext *getThreadContext(ContextID tid) 2025713Shsul@eecs.umich.edu { 2035713Shsul@eecs.umich.edu return threadContexts[tid]; 2045713Shsul@eecs.umich.edu } 2055713Shsul@eecs.umich.edu 2065714Shsul@eecs.umich.edu int numContexts() 2071806SN/A { 2086227Snate@binkert.org assert(_numContexts == (int)threadContexts.size()); 2095714Shsul@eecs.umich.edu return _numContexts; 2101806SN/A } 211180SN/A 2126029Ssteve.reinhardt@amd.com /** Return number of running (non-halted) thread contexts in 2136029Ssteve.reinhardt@amd.com * system. These threads could be Active or Suspended. */ 2146029Ssteve.reinhardt@amd.com int numRunningContexts(); 2156029Ssteve.reinhardt@amd.com 2168765Sgblack@eecs.umich.edu Addr pagePtr; 2178765Sgblack@eecs.umich.edu 2182378SN/A uint64_t init_param; 2192378SN/A 2202520SN/A /** Port to physical memory used for writing object files into ram at 2212520SN/A * boot.*/ 2228852Sandreas.hansson@arm.com PortProxy physProxy; 2232520SN/A 2241885SN/A /** kernel symbol table */ 2251070SN/A SymbolTable *kernelSymtab; 226954SN/A 2271070SN/A /** Object pointer for the kernel code */ 2281070SN/A ObjectFile *kernel; 2291070SN/A 2301070SN/A /** Begining of kernel code */ 2311070SN/A Addr kernelStart; 2321070SN/A 2331070SN/A /** End of kernel code */ 2341070SN/A Addr kernelEnd; 2351070SN/A 2361070SN/A /** Entry point in the kernel to start at */ 2371070SN/A Addr kernelEntry; 2381070SN/A 2397580SAli.Saidi@arm.com /** Mask that should be anded for binary/symbol loading. 2407580SAli.Saidi@arm.com * This allows one two different OS requirements for the same ISA to be 2417580SAli.Saidi@arm.com * handled. Some OSes are compiled for a virtual address and need to be 2427580SAli.Saidi@arm.com * loaded into physical memory that starts at address 0, while other 2437580SAli.Saidi@arm.com * bare metal tools generate images that start at address 0. 2447580SAli.Saidi@arm.com */ 2457580SAli.Saidi@arm.com Addr loadAddrMask; 2467580SAli.Saidi@arm.com 24710037SARM gem5 Developers /** Offset that should be used for binary/symbol loading. 24810037SARM gem5 Developers * This further allows more flexibily than the loadAddrMask allows alone in 24910037SARM gem5 Developers * loading kernels and similar. The loadAddrOffset is applied after the 25010037SARM gem5 Developers * loadAddrMask. 25110037SARM gem5 Developers */ 25210037SARM gem5 Developers Addr loadAddrOffset; 25310037SARM gem5 Developers 2544997Sgblack@eecs.umich.edu protected: 2557770SAli.Saidi@ARM.com uint64_t nextPID; 2564997Sgblack@eecs.umich.edu 2574997Sgblack@eecs.umich.edu public: 2584997Sgblack@eecs.umich.edu uint64_t allocatePID() 2594997Sgblack@eecs.umich.edu { 2607770SAli.Saidi@ARM.com return nextPID++; 2614997Sgblack@eecs.umich.edu } 2624997Sgblack@eecs.umich.edu 2638931Sandreas.hansson@arm.com /** Get a pointer to access the physical memory of the system */ 2648931Sandreas.hansson@arm.com PhysicalMemory& getPhysMem() { return physmem; } 2658931Sandreas.hansson@arm.com 2665795Ssaidi@eecs.umich.edu /** Amount of physical memory that is still free */ 2678931Sandreas.hansson@arm.com Addr freeMemSize() const; 2685795Ssaidi@eecs.umich.edu 2695795Ssaidi@eecs.umich.edu /** Amount of physical memory that exists */ 2708931Sandreas.hansson@arm.com Addr memSize() const; 2718931Sandreas.hansson@arm.com 2728931Sandreas.hansson@arm.com /** 2738931Sandreas.hansson@arm.com * Check if a physical address is within a range of a memory that 2748931Sandreas.hansson@arm.com * is part of the global address map. 2758931Sandreas.hansson@arm.com * 2768931Sandreas.hansson@arm.com * @param addr A physical address 2778931Sandreas.hansson@arm.com * @return Whether the address corresponds to a memory 2788931Sandreas.hansson@arm.com */ 2798931Sandreas.hansson@arm.com bool isMemAddr(Addr addr) const; 2805795Ssaidi@eecs.umich.edu 28110467Sandreas.hansson@arm.com /** 28210467Sandreas.hansson@arm.com * Get the architecture. 28310467Sandreas.hansson@arm.com */ 28410467Sandreas.hansson@arm.com Arch getArch() const { return Arch::TheISA; } 28510467Sandreas.hansson@arm.com 28610466Sandreas.hansson@arm.com /** 28710466Sandreas.hansson@arm.com * Get the page bytes for the ISA. 28810466Sandreas.hansson@arm.com */ 28910466Sandreas.hansson@arm.com Addr getPageBytes() const { return TheISA::PageBytes; } 29010466Sandreas.hansson@arm.com 29110466Sandreas.hansson@arm.com /** 29210466Sandreas.hansson@arm.com * Get the number of bits worth of in-page adress for the ISA. 29310466Sandreas.hansson@arm.com */ 29410466Sandreas.hansson@arm.com Addr getPageShift() const { return TheISA::PageShift; } 29510466Sandreas.hansson@arm.com 2961885SN/A protected: 2978931Sandreas.hansson@arm.com 2988931Sandreas.hansson@arm.com PhysicalMemory physmem; 2998931Sandreas.hansson@arm.com 3004762Snate@binkert.org Enums::MemoryMode memoryMode; 3019814Sandreas.hansson@arm.com 3029814Sandreas.hansson@arm.com const unsigned int _cacheLineSize; 3039814Sandreas.hansson@arm.com 3047914SBrad.Beckmann@amd.com uint64_t workItemsBegin; 3057914SBrad.Beckmann@amd.com uint64_t workItemsEnd; 3068666SPrakash.Ramrakhyani@arm.com uint32_t numWorkIds; 3077914SBrad.Beckmann@amd.com std::vector<bool> activeCpus; 3087914SBrad.Beckmann@amd.com 3098832SAli.Saidi@ARM.com /** This array is a per-sytem list of all devices capable of issuing a 3108832SAli.Saidi@ARM.com * memory system request and an associated string for each master id. 3118832SAli.Saidi@ARM.com * It's used to uniquely id any master in the system by name for things 3128832SAli.Saidi@ARM.com * like cache statistics. 3138832SAli.Saidi@ARM.com */ 3148832SAli.Saidi@ARM.com std::vector<std::string> masterIds; 3158832SAli.Saidi@ARM.com 3167914SBrad.Beckmann@amd.com public: 3178832SAli.Saidi@ARM.com 3188832SAli.Saidi@ARM.com /** Request an id used to create a request object in the system. All objects 3198832SAli.Saidi@ARM.com * that intend to issues requests into the memory system must request an id 3208832SAli.Saidi@ARM.com * in the init() phase of startup. All master ids must be fixed by the 3218832SAli.Saidi@ARM.com * regStats() phase that immediately preceeds it. This allows objects in the 3228832SAli.Saidi@ARM.com * memory system to understand how many masters may exist and 3238832SAli.Saidi@ARM.com * appropriately name the bins of their per-master stats before the stats 3248832SAli.Saidi@ARM.com * are finalized 3258832SAli.Saidi@ARM.com */ 3268832SAli.Saidi@ARM.com MasterID getMasterId(std::string req_name); 3278832SAli.Saidi@ARM.com 3288832SAli.Saidi@ARM.com /** Get the name of an object for a given request id. 3298832SAli.Saidi@ARM.com */ 3308832SAli.Saidi@ARM.com std::string getMasterName(MasterID master_id); 3318832SAli.Saidi@ARM.com 3328832SAli.Saidi@ARM.com /** Get the number of masters registered in the system */ 3338832SAli.Saidi@ARM.com MasterID maxMasters() 3348832SAli.Saidi@ARM.com { 3358832SAli.Saidi@ARM.com return masterIds.size(); 3368832SAli.Saidi@ARM.com } 3378832SAli.Saidi@ARM.com 3388666SPrakash.Ramrakhyani@arm.com virtual void regStats(); 3397914SBrad.Beckmann@amd.com /** 3407914SBrad.Beckmann@amd.com * Called by pseudo_inst to track the number of work items started by this 3417914SBrad.Beckmann@amd.com * system. 3427914SBrad.Beckmann@amd.com */ 3438666SPrakash.Ramrakhyani@arm.com uint64_t 3447914SBrad.Beckmann@amd.com incWorkItemsBegin() 3457914SBrad.Beckmann@amd.com { 3467914SBrad.Beckmann@amd.com return ++workItemsBegin; 3477914SBrad.Beckmann@amd.com } 3487914SBrad.Beckmann@amd.com 3497914SBrad.Beckmann@amd.com /** 3507914SBrad.Beckmann@amd.com * Called by pseudo_inst to track the number of work items completed by 3517914SBrad.Beckmann@amd.com * this system. 3527914SBrad.Beckmann@amd.com */ 35310037SARM gem5 Developers uint64_t 3547914SBrad.Beckmann@amd.com incWorkItemsEnd() 3557914SBrad.Beckmann@amd.com { 3567914SBrad.Beckmann@amd.com return ++workItemsEnd; 3577914SBrad.Beckmann@amd.com } 3587914SBrad.Beckmann@amd.com 3597914SBrad.Beckmann@amd.com /** 3607914SBrad.Beckmann@amd.com * Called by pseudo_inst to mark the cpus actively executing work items. 3617914SBrad.Beckmann@amd.com * Returns the total number of cpus that have executed work item begin or 3627914SBrad.Beckmann@amd.com * ends. 3637914SBrad.Beckmann@amd.com */ 36410037SARM gem5 Developers int 3657914SBrad.Beckmann@amd.com markWorkItem(int index) 3667914SBrad.Beckmann@amd.com { 3677914SBrad.Beckmann@amd.com int count = 0; 3687914SBrad.Beckmann@amd.com assert(index < activeCpus.size()); 3697914SBrad.Beckmann@amd.com activeCpus[index] = true; 37010037SARM gem5 Developers for (std::vector<bool>::iterator i = activeCpus.begin(); 3717914SBrad.Beckmann@amd.com i < activeCpus.end(); i++) { 3727914SBrad.Beckmann@amd.com if (*i) count++; 3737914SBrad.Beckmann@amd.com } 3747914SBrad.Beckmann@amd.com return count; 3757914SBrad.Beckmann@amd.com } 3762901Ssaidi@eecs.umich.edu 3778666SPrakash.Ramrakhyani@arm.com inline void workItemBegin(uint32_t tid, uint32_t workid) 3788666SPrakash.Ramrakhyani@arm.com { 3798666SPrakash.Ramrakhyani@arm.com std::pair<uint32_t,uint32_t> p(tid, workid); 3808666SPrakash.Ramrakhyani@arm.com lastWorkItemStarted[p] = curTick(); 3818666SPrakash.Ramrakhyani@arm.com } 3828666SPrakash.Ramrakhyani@arm.com 3838666SPrakash.Ramrakhyani@arm.com void workItemEnd(uint32_t tid, uint32_t workid); 3848666SPrakash.Ramrakhyani@arm.com 3851885SN/A /** 3861885SN/A * Fix up an address used to match PCs for hooking simulator 3871885SN/A * events on to target function executions. See comment in 3881885SN/A * system.cc for details. 3891885SN/A */ 3908769Sgblack@eecs.umich.edu virtual Addr fixFuncEventAddr(Addr addr) 3918769Sgblack@eecs.umich.edu { 3928769Sgblack@eecs.umich.edu panic("Base fixFuncEventAddr not implemented.\n"); 3938769Sgblack@eecs.umich.edu } 3941885SN/A 3959645SAndreas.Sandberg@ARM.com /** @{ */ 3961885SN/A /** 3971885SN/A * Add a function-based event to the given function, to be looked 3981885SN/A * up in the specified symbol table. 3999645SAndreas.Sandberg@ARM.com * 4009645SAndreas.Sandberg@ARM.com * The ...OrPanic flavor of the method causes the simulator to 4019645SAndreas.Sandberg@ARM.com * panic if the symbol can't be found. 4029645SAndreas.Sandberg@ARM.com * 4039645SAndreas.Sandberg@ARM.com * @param symtab Symbol table to use for look up. 4049645SAndreas.Sandberg@ARM.com * @param lbl Function to hook the event to. 4059645SAndreas.Sandberg@ARM.com * @param desc Description to be passed to the event. 4069645SAndreas.Sandberg@ARM.com * @param args Arguments to be forwarded to the event constructor. 4071885SN/A */ 4089645SAndreas.Sandberg@ARM.com template <class T, typename... Args> 4099645SAndreas.Sandberg@ARM.com T *addFuncEvent(const SymbolTable *symtab, const char *lbl, 4109645SAndreas.Sandberg@ARM.com const std::string &desc, Args... args) 4111885SN/A { 4129855Sandreas.hansson@arm.com Addr addr M5_VAR_USED = 0; // initialize only to avoid compiler warning 4131885SN/A 4149850Sandreas.hansson@arm.com#if THE_ISA != NULL_ISA 4151885SN/A if (symtab->findAddress(lbl, addr)) { 4169645SAndreas.Sandberg@ARM.com T *ev = new T(&pcEventQueue, desc, fixFuncEventAddr(addr), 4179645SAndreas.Sandberg@ARM.com std::forward<Args>(args)...); 4181885SN/A return ev; 4191885SN/A } 4209850Sandreas.hansson@arm.com#endif 4211885SN/A 4221885SN/A return NULL; 4231885SN/A } 4241885SN/A 4251885SN/A template <class T> 4269645SAndreas.Sandberg@ARM.com T *addFuncEvent(const SymbolTable *symtab, const char *lbl) 4271885SN/A { 4289645SAndreas.Sandberg@ARM.com return addFuncEvent<T>(symtab, lbl, lbl); 4291885SN/A } 4301885SN/A 4319645SAndreas.Sandberg@ARM.com template <class T, typename... Args> 4329645SAndreas.Sandberg@ARM.com T *addFuncEventOrPanic(const SymbolTable *symtab, const char *lbl, 4339645SAndreas.Sandberg@ARM.com Args... args) 4349645SAndreas.Sandberg@ARM.com { 4359645SAndreas.Sandberg@ARM.com T *e(addFuncEvent<T>(symtab, lbl, std::forward<Args>(args)...)); 4369645SAndreas.Sandberg@ARM.com if (!e) 4379645SAndreas.Sandberg@ARM.com panic("Failed to find symbol '%s'", lbl); 4389645SAndreas.Sandberg@ARM.com return e; 4399645SAndreas.Sandberg@ARM.com } 4409645SAndreas.Sandberg@ARM.com /** @} */ 4419645SAndreas.Sandberg@ARM.com 4429645SAndreas.Sandberg@ARM.com /** @{ */ 4439645SAndreas.Sandberg@ARM.com /** 4449645SAndreas.Sandberg@ARM.com * Add a function-based event to a kernel symbol. 4459645SAndreas.Sandberg@ARM.com * 4469645SAndreas.Sandberg@ARM.com * These functions work like their addFuncEvent() and 4479645SAndreas.Sandberg@ARM.com * addFuncEventOrPanic() counterparts. The only difference is that 4489645SAndreas.Sandberg@ARM.com * they automatically use the kernel symbol table. All arguments 4499645SAndreas.Sandberg@ARM.com * are forwarded to the underlying method. 4509645SAndreas.Sandberg@ARM.com * 4519645SAndreas.Sandberg@ARM.com * @see addFuncEvent() 4529645SAndreas.Sandberg@ARM.com * @see addFuncEventOrPanic() 4539645SAndreas.Sandberg@ARM.com * 4549645SAndreas.Sandberg@ARM.com * @param lbl Function to hook the event to. 4559645SAndreas.Sandberg@ARM.com * @param args Arguments to be passed to addFuncEvent 4569645SAndreas.Sandberg@ARM.com */ 4579645SAndreas.Sandberg@ARM.com template <class T, typename... Args> 4589645SAndreas.Sandberg@ARM.com T *addKernelFuncEvent(const char *lbl, Args... args) 4599645SAndreas.Sandberg@ARM.com { 4609645SAndreas.Sandberg@ARM.com return addFuncEvent<T>(kernelSymtab, lbl, 4619645SAndreas.Sandberg@ARM.com std::forward<Args>(args)...); 4629645SAndreas.Sandberg@ARM.com } 4639645SAndreas.Sandberg@ARM.com 4649645SAndreas.Sandberg@ARM.com template <class T, typename... Args> 4659645SAndreas.Sandberg@ARM.com T *addKernelFuncEventOrPanic(const char *lbl, Args... args) 4669645SAndreas.Sandberg@ARM.com { 4679645SAndreas.Sandberg@ARM.com T *e(addFuncEvent<T>(kernelSymtab, lbl, 4689645SAndreas.Sandberg@ARM.com std::forward<Args>(args)...)); 4699645SAndreas.Sandberg@ARM.com if (!e) 4709645SAndreas.Sandberg@ARM.com panic("Failed to find kernel symbol '%s'", lbl); 4719645SAndreas.Sandberg@ARM.com return e; 4729645SAndreas.Sandberg@ARM.com } 4739645SAndreas.Sandberg@ARM.com /** @} */ 4749645SAndreas.Sandberg@ARM.com 47577SN/A public: 4766658Snate@binkert.org std::vector<BaseRemoteGDB *> remoteGDB; 4771070SN/A std::vector<GDBListener *> gdbListen; 4783960Sgblack@eecs.umich.edu bool breakpoint(); 4791070SN/A 4801070SN/A public: 4814762Snate@binkert.org typedef SystemParams Params; 4821070SN/A 4832158SN/A protected: 4842158SN/A Params *_params; 4851070SN/A 4862158SN/A public: 4871070SN/A System(Params *p); 4882SN/A ~System(); 4892SN/A 4907733SAli.Saidi@ARM.com void initState(); 4911129SN/A 4922158SN/A const Params *params() const { return (const Params *)_params; } 4932158SN/A 4941070SN/A public: 4952378SN/A 4961070SN/A /** 4971070SN/A * Returns the addess the kernel starts at. 4981070SN/A * @return address the kernel starts at 4991070SN/A */ 5001070SN/A Addr getKernelStart() const { return kernelStart; } 5011070SN/A 5021070SN/A /** 5031070SN/A * Returns the addess the kernel ends at. 5041070SN/A * @return address the kernel ends at 5051070SN/A */ 5061070SN/A Addr getKernelEnd() const { return kernelEnd; } 5071070SN/A 5081070SN/A /** 5091070SN/A * Returns the addess the entry point to the kernel code. 5101070SN/A * @return entry point of the kernel code 5111070SN/A */ 5121070SN/A Addr getKernelEntry() const { return kernelEntry; } 5131070SN/A 5148601Ssteve.reinhardt@amd.com /// Allocate npages contiguous unused physical pages 5158601Ssteve.reinhardt@amd.com /// @return Starting address of first page 5168601Ssteve.reinhardt@amd.com Addr allocPhysPages(int npages); 5172378SN/A 51811005Sandreas.sandberg@arm.com ContextID registerThreadContext(ThreadContext *tc, 51911005Sandreas.sandberg@arm.com ContextID assigned = InvalidContextID); 52011005Sandreas.sandberg@arm.com void replaceThreadContext(ThreadContext *tc, ContextID context_id); 5211070SN/A 52211168Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 52311168Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 5249342SAndreas.Sandberg@arm.com 52511168Sandreas.hansson@arm.com void drainResume() override; 5262SN/A 52777SN/A public: 5287897Shestness@cs.utexas.edu Counter totalNumInsts; 5297897Shestness@cs.utexas.edu EventQueue instEventQueue; 5308666SPrakash.Ramrakhyani@arm.com std::map<std::pair<uint32_t,uint32_t>, Tick> lastWorkItemStarted; 5318666SPrakash.Ramrakhyani@arm.com std::map<uint32_t, Stats::Histogram*> workItemStats; 5327897Shestness@cs.utexas.edu 5332SN/A //////////////////////////////////////////// 5342SN/A // 5352SN/A // STATIC GLOBAL SYSTEM LIST 5362SN/A // 5372SN/A //////////////////////////////////////////// 5382SN/A 5392SN/A static std::vector<System *> systemList; 5402SN/A static int numSystemsRunning; 5412SN/A 5422SN/A static void printSystems(); 5432158SN/A 5449112Smarc.orr@gmail.com // For futex system call 5459112Smarc.orr@gmail.com std::map<uint64_t, std::list<ThreadContext *> * > futexMap; 5469112Smarc.orr@gmail.com 5479292Sandreas.hansson@arm.com protected: 5489292Sandreas.hansson@arm.com 5499292Sandreas.hansson@arm.com /** 5509292Sandreas.hansson@arm.com * If needed, serialize additional symbol table entries for a 5519292Sandreas.hansson@arm.com * specific subclass of this sytem. Currently this is used by 5529292Sandreas.hansson@arm.com * Alpha and MIPS. 5539292Sandreas.hansson@arm.com * 5549292Sandreas.hansson@arm.com * @param os stream to serialize to 5559292Sandreas.hansson@arm.com */ 55610905Sandreas.sandberg@arm.com virtual void serializeSymtab(CheckpointOut &os) const {} 5579292Sandreas.hansson@arm.com 5589292Sandreas.hansson@arm.com /** 5599292Sandreas.hansson@arm.com * If needed, unserialize additional symbol table entries for a 5609292Sandreas.hansson@arm.com * specific subclass of this system. 5619292Sandreas.hansson@arm.com * 5629292Sandreas.hansson@arm.com * @param cp checkpoint to unserialize from 5639292Sandreas.hansson@arm.com * @param section relevant section in the checkpoint 5649292Sandreas.hansson@arm.com */ 56510905Sandreas.sandberg@arm.com virtual void unserializeSymtab(CheckpointIn &cp) {} 5662158SN/A 5672SN/A}; 5682SN/A 5699554Sandreas.hansson@arm.comvoid printSystems(); 5709554Sandreas.hansson@arm.com 5712SN/A#endif // __SYSTEM_HH__ 572