system.hh revision 10467
12SN/A/* 210466Sandreas.hansson@arm.com * Copyright (c) 2012, 2014 ARM Limited 38703Sandreas.hansson@arm.com * All rights reserved 48703Sandreas.hansson@arm.com * 58703Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68703Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78703Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88703Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98703Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108703Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118703Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128703Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138703Sandreas.hansson@arm.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422665Ssaidi@eecs.umich.edu * Lisa Hsu 432665Ssaidi@eecs.umich.edu * Nathan Binkert 447897Shestness@cs.utexas.edu * Rick Strong 452SN/A */ 462SN/A 472SN/A#ifndef __SYSTEM_HH__ 482SN/A#define __SYSTEM_HH__ 492SN/A 502SN/A#include <string> 519645SAndreas.Sandberg@ARM.com#include <utility> 5275SN/A#include <vector> 532SN/A 5410466Sandreas.hansson@arm.com#include "arch/isa_traits.hh" 552439SN/A#include "base/loader/symtab.hh" 562439SN/A#include "base/misc.hh" 57603SN/A#include "base/statistics.hh" 5810466Sandreas.hansson@arm.com#include "config/the_isa.hh" 59603SN/A#include "cpu/pc_event.hh" 604762Snate@binkert.org#include "enums/MemoryMode.hh" 618769Sgblack@eecs.umich.edu#include "kern/system_events.hh" 628703Sandreas.hansson@arm.com#include "mem/mem_object.hh" 632520SN/A#include "mem/port.hh" 649847Sandreas.hansson@arm.com#include "mem/port_proxy.hh" 658931Sandreas.hansson@arm.com#include "mem/physical.hh" 664762Snate@binkert.org#include "params/System.hh" 676658Snate@binkert.org 681634SN/Aclass BaseCPU; 698769Sgblack@eecs.umich.educlass BaseRemoteGDB; 708769Sgblack@eecs.umich.educlass GDBListener; 711634SN/Aclass ObjectFile; 72803SN/Aclass Platform; 738769Sgblack@eecs.umich.educlass ThreadContext; 742SN/A 758703Sandreas.hansson@arm.comclass System : public MemObject 762SN/A{ 778703Sandreas.hansson@arm.com private: 788703Sandreas.hansson@arm.com 798703Sandreas.hansson@arm.com /** 808703Sandreas.hansson@arm.com * Private class for the system port which is only used as a 818703Sandreas.hansson@arm.com * master for debug access and for non-structural entities that do 828703Sandreas.hansson@arm.com * not have a port of their own. 838703Sandreas.hansson@arm.com */ 848922Swilliam.wang@arm.com class SystemPort : public MasterPort 858703Sandreas.hansson@arm.com { 868703Sandreas.hansson@arm.com public: 878703Sandreas.hansson@arm.com 888703Sandreas.hansson@arm.com /** 898703Sandreas.hansson@arm.com * Create a system port with a name and an owner. 908703Sandreas.hansson@arm.com */ 918703Sandreas.hansson@arm.com SystemPort(const std::string &_name, MemObject *_owner) 928922Swilliam.wang@arm.com : MasterPort(_name, _owner) 938703Sandreas.hansson@arm.com { } 948975Sandreas.hansson@arm.com bool recvTimingResp(PacketPtr pkt) 958703Sandreas.hansson@arm.com { panic("SystemPort does not receive timing!\n"); return false; } 968922Swilliam.wang@arm.com void recvRetry() 978922Swilliam.wang@arm.com { panic("SystemPort does not expect retry!\n"); } 988703Sandreas.hansson@arm.com }; 998703Sandreas.hansson@arm.com 1008703Sandreas.hansson@arm.com SystemPort _systemPort; 1018703Sandreas.hansson@arm.com 102603SN/A public: 1032901Ssaidi@eecs.umich.edu 1048703Sandreas.hansson@arm.com /** 1058706Sandreas.hansson@arm.com * After all objects have been created and all ports are 1068706Sandreas.hansson@arm.com * connected, check that the system port is connected. 1078706Sandreas.hansson@arm.com */ 1088706Sandreas.hansson@arm.com virtual void init(); 1098706Sandreas.hansson@arm.com 1108706Sandreas.hansson@arm.com /** 1118852Sandreas.hansson@arm.com * Get a reference to the system port that can be used by 1128703Sandreas.hansson@arm.com * non-structural simulation objects like processes or threads, or 1138703Sandreas.hansson@arm.com * external entities like loaders and debuggers, etc, to access 1148703Sandreas.hansson@arm.com * the memory system. 1158703Sandreas.hansson@arm.com * 1168852Sandreas.hansson@arm.com * @return a reference to the system port we own 1178703Sandreas.hansson@arm.com */ 1188922Swilliam.wang@arm.com MasterPort& getSystemPort() { return _systemPort; } 1198703Sandreas.hansson@arm.com 1208703Sandreas.hansson@arm.com /** 1218703Sandreas.hansson@arm.com * Additional function to return the Port of a memory object. 1228703Sandreas.hansson@arm.com */ 1239294Sandreas.hansson@arm.com BaseMasterPort& getMasterPort(const std::string &if_name, 1249294Sandreas.hansson@arm.com PortID idx = InvalidPortID); 1258703Sandreas.hansson@arm.com 1269524SAndreas.Sandberg@ARM.com /** @{ */ 1279524SAndreas.Sandberg@ARM.com /** 1289524SAndreas.Sandberg@ARM.com * Is the system in atomic mode? 1299524SAndreas.Sandberg@ARM.com * 1309524SAndreas.Sandberg@ARM.com * There are currently two different atomic memory modes: 1319524SAndreas.Sandberg@ARM.com * 'atomic', which supports caches; and 'atomic_noncaching', which 1329524SAndreas.Sandberg@ARM.com * bypasses caches. The latter is used by hardware virtualized 1339524SAndreas.Sandberg@ARM.com * CPUs. SimObjects are expected to use Port::sendAtomic() and 1349524SAndreas.Sandberg@ARM.com * Port::recvAtomic() when accessing memory in this mode. 1359524SAndreas.Sandberg@ARM.com */ 1369524SAndreas.Sandberg@ARM.com bool isAtomicMode() const { 1379524SAndreas.Sandberg@ARM.com return memoryMode == Enums::atomic || 1389524SAndreas.Sandberg@ARM.com memoryMode == Enums::atomic_noncaching; 1394762Snate@binkert.org } 1402901Ssaidi@eecs.umich.edu 1419524SAndreas.Sandberg@ARM.com /** 1429524SAndreas.Sandberg@ARM.com * Is the system in timing mode? 1439524SAndreas.Sandberg@ARM.com * 1449524SAndreas.Sandberg@ARM.com * SimObjects are expected to use Port::sendTiming() and 1459524SAndreas.Sandberg@ARM.com * Port::recvTiming() when accessing memory in this mode. 1469524SAndreas.Sandberg@ARM.com */ 1479524SAndreas.Sandberg@ARM.com bool isTimingMode() const { 1489524SAndreas.Sandberg@ARM.com return memoryMode == Enums::timing; 1499524SAndreas.Sandberg@ARM.com } 1509524SAndreas.Sandberg@ARM.com 1519524SAndreas.Sandberg@ARM.com /** 1529524SAndreas.Sandberg@ARM.com * Should caches be bypassed? 1539524SAndreas.Sandberg@ARM.com * 1549524SAndreas.Sandberg@ARM.com * Some CPUs need to bypass caches to allow direct memory 1559524SAndreas.Sandberg@ARM.com * accesses, which is required for hardware virtualization. 1569524SAndreas.Sandberg@ARM.com */ 1579524SAndreas.Sandberg@ARM.com bool bypassCaches() const { 1589524SAndreas.Sandberg@ARM.com return memoryMode == Enums::atomic_noncaching; 1599524SAndreas.Sandberg@ARM.com } 1609524SAndreas.Sandberg@ARM.com /** @} */ 1619524SAndreas.Sandberg@ARM.com 1629524SAndreas.Sandberg@ARM.com /** @{ */ 1639524SAndreas.Sandberg@ARM.com /** 1649524SAndreas.Sandberg@ARM.com * Get the memory mode of the system. 1659524SAndreas.Sandberg@ARM.com * 1669524SAndreas.Sandberg@ARM.com * \warn This should only be used by the Python world. The C++ 1679524SAndreas.Sandberg@ARM.com * world should use one of the query functions above 1689524SAndreas.Sandberg@ARM.com * (isAtomicMode(), isTimingMode(), bypassCaches()). 1699524SAndreas.Sandberg@ARM.com */ 1709524SAndreas.Sandberg@ARM.com Enums::MemoryMode getMemoryMode() const { return memoryMode; } 1719524SAndreas.Sandberg@ARM.com 1729524SAndreas.Sandberg@ARM.com /** 1739524SAndreas.Sandberg@ARM.com * Change the memory mode of the system. 1749524SAndreas.Sandberg@ARM.com * 1759524SAndreas.Sandberg@ARM.com * \warn This should only be called by the Python! 1769524SAndreas.Sandberg@ARM.com * 1779524SAndreas.Sandberg@ARM.com * @param mode Mode to change to (atomic/timing/...) 1782901Ssaidi@eecs.umich.edu */ 1794762Snate@binkert.org void setMemoryMode(Enums::MemoryMode mode); 1809524SAndreas.Sandberg@ARM.com /** @} */ 1812901Ssaidi@eecs.umich.edu 1829814Sandreas.hansson@arm.com /** 1839814Sandreas.hansson@arm.com * Get the cache line size of the system. 1849814Sandreas.hansson@arm.com */ 1859814Sandreas.hansson@arm.com unsigned int cacheLineSize() const { return _cacheLineSize; } 1869814Sandreas.hansson@arm.com 1879850Sandreas.hansson@arm.com#if THE_ISA != NULL_ISA 1882SN/A PCEventQueue pcEventQueue; 1899850Sandreas.hansson@arm.com#endif 1902SN/A 1912680Sktlim@umich.edu std::vector<ThreadContext *> threadContexts; 1925714Shsul@eecs.umich.edu int _numContexts; 1931806SN/A 1946221Snate@binkert.org ThreadContext *getThreadContext(ThreadID tid) 1955713Shsul@eecs.umich.edu { 1965713Shsul@eecs.umich.edu return threadContexts[tid]; 1975713Shsul@eecs.umich.edu } 1985713Shsul@eecs.umich.edu 1995714Shsul@eecs.umich.edu int numContexts() 2001806SN/A { 2016227Snate@binkert.org assert(_numContexts == (int)threadContexts.size()); 2025714Shsul@eecs.umich.edu return _numContexts; 2031806SN/A } 204180SN/A 2056029Ssteve.reinhardt@amd.com /** Return number of running (non-halted) thread contexts in 2066029Ssteve.reinhardt@amd.com * system. These threads could be Active or Suspended. */ 2076029Ssteve.reinhardt@amd.com int numRunningContexts(); 2086029Ssteve.reinhardt@amd.com 2098765Sgblack@eecs.umich.edu Addr pagePtr; 2108765Sgblack@eecs.umich.edu 2112378SN/A uint64_t init_param; 2122378SN/A 2132520SN/A /** Port to physical memory used for writing object files into ram at 2142520SN/A * boot.*/ 2158852Sandreas.hansson@arm.com PortProxy physProxy; 2162520SN/A 2171885SN/A /** kernel symbol table */ 2181070SN/A SymbolTable *kernelSymtab; 219954SN/A 2201070SN/A /** Object pointer for the kernel code */ 2211070SN/A ObjectFile *kernel; 2221070SN/A 2231070SN/A /** Begining of kernel code */ 2241070SN/A Addr kernelStart; 2251070SN/A 2261070SN/A /** End of kernel code */ 2271070SN/A Addr kernelEnd; 2281070SN/A 2291070SN/A /** Entry point in the kernel to start at */ 2301070SN/A Addr kernelEntry; 2311070SN/A 2327580SAli.Saidi@arm.com /** Mask that should be anded for binary/symbol loading. 2337580SAli.Saidi@arm.com * This allows one two different OS requirements for the same ISA to be 2347580SAli.Saidi@arm.com * handled. Some OSes are compiled for a virtual address and need to be 2357580SAli.Saidi@arm.com * loaded into physical memory that starts at address 0, while other 2367580SAli.Saidi@arm.com * bare metal tools generate images that start at address 0. 2377580SAli.Saidi@arm.com */ 2387580SAli.Saidi@arm.com Addr loadAddrMask; 2397580SAli.Saidi@arm.com 24010037SARM gem5 Developers /** Offset that should be used for binary/symbol loading. 24110037SARM gem5 Developers * This further allows more flexibily than the loadAddrMask allows alone in 24210037SARM gem5 Developers * loading kernels and similar. The loadAddrOffset is applied after the 24310037SARM gem5 Developers * loadAddrMask. 24410037SARM gem5 Developers */ 24510037SARM gem5 Developers Addr loadAddrOffset; 24610037SARM gem5 Developers 2474997Sgblack@eecs.umich.edu protected: 2487770SAli.Saidi@ARM.com uint64_t nextPID; 2494997Sgblack@eecs.umich.edu 2504997Sgblack@eecs.umich.edu public: 2514997Sgblack@eecs.umich.edu uint64_t allocatePID() 2524997Sgblack@eecs.umich.edu { 2537770SAli.Saidi@ARM.com return nextPID++; 2544997Sgblack@eecs.umich.edu } 2554997Sgblack@eecs.umich.edu 2568931Sandreas.hansson@arm.com /** Get a pointer to access the physical memory of the system */ 2578931Sandreas.hansson@arm.com PhysicalMemory& getPhysMem() { return physmem; } 2588931Sandreas.hansson@arm.com 2595795Ssaidi@eecs.umich.edu /** Amount of physical memory that is still free */ 2608931Sandreas.hansson@arm.com Addr freeMemSize() const; 2615795Ssaidi@eecs.umich.edu 2625795Ssaidi@eecs.umich.edu /** Amount of physical memory that exists */ 2638931Sandreas.hansson@arm.com Addr memSize() const; 2648931Sandreas.hansson@arm.com 2658931Sandreas.hansson@arm.com /** 2668931Sandreas.hansson@arm.com * Check if a physical address is within a range of a memory that 2678931Sandreas.hansson@arm.com * is part of the global address map. 2688931Sandreas.hansson@arm.com * 2698931Sandreas.hansson@arm.com * @param addr A physical address 2708931Sandreas.hansson@arm.com * @return Whether the address corresponds to a memory 2718931Sandreas.hansson@arm.com */ 2728931Sandreas.hansson@arm.com bool isMemAddr(Addr addr) const; 2735795Ssaidi@eecs.umich.edu 27410467Sandreas.hansson@arm.com /** 27510467Sandreas.hansson@arm.com * Get the architecture. 27610467Sandreas.hansson@arm.com */ 27710467Sandreas.hansson@arm.com Arch getArch() const { return Arch::TheISA; } 27810467Sandreas.hansson@arm.com 27910466Sandreas.hansson@arm.com /** 28010466Sandreas.hansson@arm.com * Get the page bytes for the ISA. 28110466Sandreas.hansson@arm.com */ 28210466Sandreas.hansson@arm.com Addr getPageBytes() const { return TheISA::PageBytes; } 28310466Sandreas.hansson@arm.com 28410466Sandreas.hansson@arm.com /** 28510466Sandreas.hansson@arm.com * Get the number of bits worth of in-page adress for the ISA. 28610466Sandreas.hansson@arm.com */ 28710466Sandreas.hansson@arm.com Addr getPageShift() const { return TheISA::PageShift; } 28810466Sandreas.hansson@arm.com 2891885SN/A protected: 2908931Sandreas.hansson@arm.com 2918931Sandreas.hansson@arm.com PhysicalMemory physmem; 2928931Sandreas.hansson@arm.com 2934762Snate@binkert.org Enums::MemoryMode memoryMode; 2949814Sandreas.hansson@arm.com 2959814Sandreas.hansson@arm.com const unsigned int _cacheLineSize; 2969814Sandreas.hansson@arm.com 2977914SBrad.Beckmann@amd.com uint64_t workItemsBegin; 2987914SBrad.Beckmann@amd.com uint64_t workItemsEnd; 2998666SPrakash.Ramrakhyani@arm.com uint32_t numWorkIds; 3007914SBrad.Beckmann@amd.com std::vector<bool> activeCpus; 3017914SBrad.Beckmann@amd.com 3028832SAli.Saidi@ARM.com /** This array is a per-sytem list of all devices capable of issuing a 3038832SAli.Saidi@ARM.com * memory system request and an associated string for each master id. 3048832SAli.Saidi@ARM.com * It's used to uniquely id any master in the system by name for things 3058832SAli.Saidi@ARM.com * like cache statistics. 3068832SAli.Saidi@ARM.com */ 3078832SAli.Saidi@ARM.com std::vector<std::string> masterIds; 3088832SAli.Saidi@ARM.com 3097914SBrad.Beckmann@amd.com public: 3108832SAli.Saidi@ARM.com 3118832SAli.Saidi@ARM.com /** Request an id used to create a request object in the system. All objects 3128832SAli.Saidi@ARM.com * that intend to issues requests into the memory system must request an id 3138832SAli.Saidi@ARM.com * in the init() phase of startup. All master ids must be fixed by the 3148832SAli.Saidi@ARM.com * regStats() phase that immediately preceeds it. This allows objects in the 3158832SAli.Saidi@ARM.com * memory system to understand how many masters may exist and 3168832SAli.Saidi@ARM.com * appropriately name the bins of their per-master stats before the stats 3178832SAli.Saidi@ARM.com * are finalized 3188832SAli.Saidi@ARM.com */ 3198832SAli.Saidi@ARM.com MasterID getMasterId(std::string req_name); 3208832SAli.Saidi@ARM.com 3218832SAli.Saidi@ARM.com /** Get the name of an object for a given request id. 3228832SAli.Saidi@ARM.com */ 3238832SAli.Saidi@ARM.com std::string getMasterName(MasterID master_id); 3248832SAli.Saidi@ARM.com 3258832SAli.Saidi@ARM.com /** Get the number of masters registered in the system */ 3268832SAli.Saidi@ARM.com MasterID maxMasters() 3278832SAli.Saidi@ARM.com { 3288832SAli.Saidi@ARM.com return masterIds.size(); 3298832SAli.Saidi@ARM.com } 3308832SAli.Saidi@ARM.com 3318666SPrakash.Ramrakhyani@arm.com virtual void regStats(); 3327914SBrad.Beckmann@amd.com /** 3337914SBrad.Beckmann@amd.com * Called by pseudo_inst to track the number of work items started by this 3347914SBrad.Beckmann@amd.com * system. 3357914SBrad.Beckmann@amd.com */ 3368666SPrakash.Ramrakhyani@arm.com uint64_t 3377914SBrad.Beckmann@amd.com incWorkItemsBegin() 3387914SBrad.Beckmann@amd.com { 3397914SBrad.Beckmann@amd.com return ++workItemsBegin; 3407914SBrad.Beckmann@amd.com } 3417914SBrad.Beckmann@amd.com 3427914SBrad.Beckmann@amd.com /** 3437914SBrad.Beckmann@amd.com * Called by pseudo_inst to track the number of work items completed by 3447914SBrad.Beckmann@amd.com * this system. 3457914SBrad.Beckmann@amd.com */ 34610037SARM gem5 Developers uint64_t 3477914SBrad.Beckmann@amd.com incWorkItemsEnd() 3487914SBrad.Beckmann@amd.com { 3497914SBrad.Beckmann@amd.com return ++workItemsEnd; 3507914SBrad.Beckmann@amd.com } 3517914SBrad.Beckmann@amd.com 3527914SBrad.Beckmann@amd.com /** 3537914SBrad.Beckmann@amd.com * Called by pseudo_inst to mark the cpus actively executing work items. 3547914SBrad.Beckmann@amd.com * Returns the total number of cpus that have executed work item begin or 3557914SBrad.Beckmann@amd.com * ends. 3567914SBrad.Beckmann@amd.com */ 35710037SARM gem5 Developers int 3587914SBrad.Beckmann@amd.com markWorkItem(int index) 3597914SBrad.Beckmann@amd.com { 3607914SBrad.Beckmann@amd.com int count = 0; 3617914SBrad.Beckmann@amd.com assert(index < activeCpus.size()); 3627914SBrad.Beckmann@amd.com activeCpus[index] = true; 36310037SARM gem5 Developers for (std::vector<bool>::iterator i = activeCpus.begin(); 3647914SBrad.Beckmann@amd.com i < activeCpus.end(); i++) { 3657914SBrad.Beckmann@amd.com if (*i) count++; 3667914SBrad.Beckmann@amd.com } 3677914SBrad.Beckmann@amd.com return count; 3687914SBrad.Beckmann@amd.com } 3692901Ssaidi@eecs.umich.edu 3708666SPrakash.Ramrakhyani@arm.com inline void workItemBegin(uint32_t tid, uint32_t workid) 3718666SPrakash.Ramrakhyani@arm.com { 3728666SPrakash.Ramrakhyani@arm.com std::pair<uint32_t,uint32_t> p(tid, workid); 3738666SPrakash.Ramrakhyani@arm.com lastWorkItemStarted[p] = curTick(); 3748666SPrakash.Ramrakhyani@arm.com } 3758666SPrakash.Ramrakhyani@arm.com 3768666SPrakash.Ramrakhyani@arm.com void workItemEnd(uint32_t tid, uint32_t workid); 3778666SPrakash.Ramrakhyani@arm.com 3781885SN/A /** 3791885SN/A * Fix up an address used to match PCs for hooking simulator 3801885SN/A * events on to target function executions. See comment in 3811885SN/A * system.cc for details. 3821885SN/A */ 3838769Sgblack@eecs.umich.edu virtual Addr fixFuncEventAddr(Addr addr) 3848769Sgblack@eecs.umich.edu { 3858769Sgblack@eecs.umich.edu panic("Base fixFuncEventAddr not implemented.\n"); 3868769Sgblack@eecs.umich.edu } 3871885SN/A 3889645SAndreas.Sandberg@ARM.com /** @{ */ 3891885SN/A /** 3901885SN/A * Add a function-based event to the given function, to be looked 3911885SN/A * up in the specified symbol table. 3929645SAndreas.Sandberg@ARM.com * 3939645SAndreas.Sandberg@ARM.com * The ...OrPanic flavor of the method causes the simulator to 3949645SAndreas.Sandberg@ARM.com * panic if the symbol can't be found. 3959645SAndreas.Sandberg@ARM.com * 3969645SAndreas.Sandberg@ARM.com * @param symtab Symbol table to use for look up. 3979645SAndreas.Sandberg@ARM.com * @param lbl Function to hook the event to. 3989645SAndreas.Sandberg@ARM.com * @param desc Description to be passed to the event. 3999645SAndreas.Sandberg@ARM.com * @param args Arguments to be forwarded to the event constructor. 4001885SN/A */ 4019645SAndreas.Sandberg@ARM.com template <class T, typename... Args> 4029645SAndreas.Sandberg@ARM.com T *addFuncEvent(const SymbolTable *symtab, const char *lbl, 4039645SAndreas.Sandberg@ARM.com const std::string &desc, Args... args) 4041885SN/A { 4059855Sandreas.hansson@arm.com Addr addr M5_VAR_USED = 0; // initialize only to avoid compiler warning 4061885SN/A 4079850Sandreas.hansson@arm.com#if THE_ISA != NULL_ISA 4081885SN/A if (symtab->findAddress(lbl, addr)) { 4099645SAndreas.Sandberg@ARM.com T *ev = new T(&pcEventQueue, desc, fixFuncEventAddr(addr), 4109645SAndreas.Sandberg@ARM.com std::forward<Args>(args)...); 4111885SN/A return ev; 4121885SN/A } 4139850Sandreas.hansson@arm.com#endif 4141885SN/A 4151885SN/A return NULL; 4161885SN/A } 4171885SN/A 4181885SN/A template <class T> 4199645SAndreas.Sandberg@ARM.com T *addFuncEvent(const SymbolTable *symtab, const char *lbl) 4201885SN/A { 4219645SAndreas.Sandberg@ARM.com return addFuncEvent<T>(symtab, lbl, lbl); 4221885SN/A } 4231885SN/A 4249645SAndreas.Sandberg@ARM.com template <class T, typename... Args> 4259645SAndreas.Sandberg@ARM.com T *addFuncEventOrPanic(const SymbolTable *symtab, const char *lbl, 4269645SAndreas.Sandberg@ARM.com Args... args) 4279645SAndreas.Sandberg@ARM.com { 4289645SAndreas.Sandberg@ARM.com T *e(addFuncEvent<T>(symtab, lbl, std::forward<Args>(args)...)); 4299645SAndreas.Sandberg@ARM.com if (!e) 4309645SAndreas.Sandberg@ARM.com panic("Failed to find symbol '%s'", lbl); 4319645SAndreas.Sandberg@ARM.com return e; 4329645SAndreas.Sandberg@ARM.com } 4339645SAndreas.Sandberg@ARM.com /** @} */ 4349645SAndreas.Sandberg@ARM.com 4359645SAndreas.Sandberg@ARM.com /** @{ */ 4369645SAndreas.Sandberg@ARM.com /** 4379645SAndreas.Sandberg@ARM.com * Add a function-based event to a kernel symbol. 4389645SAndreas.Sandberg@ARM.com * 4399645SAndreas.Sandberg@ARM.com * These functions work like their addFuncEvent() and 4409645SAndreas.Sandberg@ARM.com * addFuncEventOrPanic() counterparts. The only difference is that 4419645SAndreas.Sandberg@ARM.com * they automatically use the kernel symbol table. All arguments 4429645SAndreas.Sandberg@ARM.com * are forwarded to the underlying method. 4439645SAndreas.Sandberg@ARM.com * 4449645SAndreas.Sandberg@ARM.com * @see addFuncEvent() 4459645SAndreas.Sandberg@ARM.com * @see addFuncEventOrPanic() 4469645SAndreas.Sandberg@ARM.com * 4479645SAndreas.Sandberg@ARM.com * @param lbl Function to hook the event to. 4489645SAndreas.Sandberg@ARM.com * @param args Arguments to be passed to addFuncEvent 4499645SAndreas.Sandberg@ARM.com */ 4509645SAndreas.Sandberg@ARM.com template <class T, typename... Args> 4519645SAndreas.Sandberg@ARM.com T *addKernelFuncEvent(const char *lbl, Args... args) 4529645SAndreas.Sandberg@ARM.com { 4539645SAndreas.Sandberg@ARM.com return addFuncEvent<T>(kernelSymtab, lbl, 4549645SAndreas.Sandberg@ARM.com std::forward<Args>(args)...); 4559645SAndreas.Sandberg@ARM.com } 4569645SAndreas.Sandberg@ARM.com 4579645SAndreas.Sandberg@ARM.com template <class T, typename... Args> 4589645SAndreas.Sandberg@ARM.com T *addKernelFuncEventOrPanic(const char *lbl, Args... args) 4599645SAndreas.Sandberg@ARM.com { 4609645SAndreas.Sandberg@ARM.com T *e(addFuncEvent<T>(kernelSymtab, lbl, 4619645SAndreas.Sandberg@ARM.com std::forward<Args>(args)...)); 4629645SAndreas.Sandberg@ARM.com if (!e) 4639645SAndreas.Sandberg@ARM.com panic("Failed to find kernel symbol '%s'", lbl); 4649645SAndreas.Sandberg@ARM.com return e; 4659645SAndreas.Sandberg@ARM.com } 4669645SAndreas.Sandberg@ARM.com /** @} */ 4679645SAndreas.Sandberg@ARM.com 46877SN/A public: 4696658Snate@binkert.org std::vector<BaseRemoteGDB *> remoteGDB; 4701070SN/A std::vector<GDBListener *> gdbListen; 4713960Sgblack@eecs.umich.edu bool breakpoint(); 4721070SN/A 4731070SN/A public: 4744762Snate@binkert.org typedef SystemParams Params; 4751070SN/A 4762158SN/A protected: 4772158SN/A Params *_params; 4781070SN/A 4792158SN/A public: 4801070SN/A System(Params *p); 4812SN/A ~System(); 4822SN/A 4837733SAli.Saidi@ARM.com void initState(); 4841129SN/A 4852158SN/A const Params *params() const { return (const Params *)_params; } 4862158SN/A 4871070SN/A public: 4882378SN/A 4891070SN/A /** 4901070SN/A * Returns the addess the kernel starts at. 4911070SN/A * @return address the kernel starts at 4921070SN/A */ 4931070SN/A Addr getKernelStart() const { return kernelStart; } 4941070SN/A 4951070SN/A /** 4961070SN/A * Returns the addess the kernel ends at. 4971070SN/A * @return address the kernel ends at 4981070SN/A */ 4991070SN/A Addr getKernelEnd() const { return kernelEnd; } 5001070SN/A 5011070SN/A /** 5021070SN/A * Returns the addess the entry point to the kernel code. 5031070SN/A * @return entry point of the kernel code 5041070SN/A */ 5051070SN/A Addr getKernelEntry() const { return kernelEntry; } 5061070SN/A 5078601Ssteve.reinhardt@amd.com /// Allocate npages contiguous unused physical pages 5088601Ssteve.reinhardt@amd.com /// @return Starting address of first page 5098601Ssteve.reinhardt@amd.com Addr allocPhysPages(int npages); 5102378SN/A 5115718Shsul@eecs.umich.edu int registerThreadContext(ThreadContext *tc, int assigned=-1); 5125713Shsul@eecs.umich.edu void replaceThreadContext(ThreadContext *tc, int context_id); 5131070SN/A 5141070SN/A void serialize(std::ostream &os); 5151070SN/A void unserialize(Checkpoint *cp, const std::string §ion); 5169342SAndreas.Sandberg@arm.com 5179342SAndreas.Sandberg@arm.com unsigned int drain(DrainManager *dm); 5189342SAndreas.Sandberg@arm.com void drainResume(); 5192SN/A 52077SN/A public: 5217897Shestness@cs.utexas.edu Counter totalNumInsts; 5227897Shestness@cs.utexas.edu EventQueue instEventQueue; 5238666SPrakash.Ramrakhyani@arm.com std::map<std::pair<uint32_t,uint32_t>, Tick> lastWorkItemStarted; 5248666SPrakash.Ramrakhyani@arm.com std::map<uint32_t, Stats::Histogram*> workItemStats; 5257897Shestness@cs.utexas.edu 5262SN/A //////////////////////////////////////////// 5272SN/A // 5282SN/A // STATIC GLOBAL SYSTEM LIST 5292SN/A // 5302SN/A //////////////////////////////////////////// 5312SN/A 5322SN/A static std::vector<System *> systemList; 5332SN/A static int numSystemsRunning; 5342SN/A 5352SN/A static void printSystems(); 5362158SN/A 5379112Smarc.orr@gmail.com // For futex system call 5389112Smarc.orr@gmail.com std::map<uint64_t, std::list<ThreadContext *> * > futexMap; 5399112Smarc.orr@gmail.com 5409292Sandreas.hansson@arm.com protected: 5419292Sandreas.hansson@arm.com 5429292Sandreas.hansson@arm.com /** 5439292Sandreas.hansson@arm.com * If needed, serialize additional symbol table entries for a 5449292Sandreas.hansson@arm.com * specific subclass of this sytem. Currently this is used by 5459292Sandreas.hansson@arm.com * Alpha and MIPS. 5469292Sandreas.hansson@arm.com * 5479292Sandreas.hansson@arm.com * @param os stream to serialize to 5489292Sandreas.hansson@arm.com */ 5499292Sandreas.hansson@arm.com virtual void serializeSymtab(std::ostream &os) {} 5509292Sandreas.hansson@arm.com 5519292Sandreas.hansson@arm.com /** 5529292Sandreas.hansson@arm.com * If needed, unserialize additional symbol table entries for a 5539292Sandreas.hansson@arm.com * specific subclass of this system. 5549292Sandreas.hansson@arm.com * 5559292Sandreas.hansson@arm.com * @param cp checkpoint to unserialize from 5569292Sandreas.hansson@arm.com * @param section relevant section in the checkpoint 5579292Sandreas.hansson@arm.com */ 5589292Sandreas.hansson@arm.com virtual void unserializeSymtab(Checkpoint *cp, 5599292Sandreas.hansson@arm.com const std::string §ion) {} 5602158SN/A 5612SN/A}; 5622SN/A 5639554Sandreas.hansson@arm.comvoid printSystems(); 5649554Sandreas.hansson@arm.com 5652SN/A#endif // __SYSTEM_HH__ 566