stat_control.cc revision 8720 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Nathan Binkert
29 */
30
31// This file will contain default statistics for the simulator that
32// don't really belong to a specific simulator object
33
34#include <fstream>
35#include <iostream>
36#include <list>
37
38#include "base/callback.hh"
39#include "base/hostinfo.hh"
40#include "base/statistics.hh"
41#include "base/time.hh"
42#include "config/the_isa.hh"
43#if THE_ISA == NO_ISA
44#include "arch/noisa/cpu_dummy.hh"
45#else
46#include "cpu/base.hh"
47#endif
48
49#include "sim/eventq.hh"
50#include "sim/stat_control.hh"
51
52using namespace std;
53
54Stats::Formula simSeconds;
55Stats::Value simTicks;
56Stats::Value finalTick;
57Stats::Value simFreq;
58
59namespace Stats {
60
61Time statTime(true);
62Tick startTick;
63
64struct SimTicksReset : public Callback
65{
66    void process()
67    {
68        statTime.setTimer();
69        startTick = curTick();
70    }
71};
72
73double
74statElapsedTime()
75{
76    Time now;
77    now.setTimer();
78
79    Time elapsed = now - statTime;
80    return elapsed;
81}
82
83Tick
84statElapsedTicks()
85{
86    return curTick() - startTick;
87}
88
89Tick
90statFinalTick()
91{
92    return curTick();
93}
94
95SimTicksReset simTicksReset;
96
97struct Global
98{
99    Stats::Formula hostInstRate;
100    Stats::Formula hostTickRate;
101    Stats::Value hostMemory;
102    Stats::Value hostSeconds;
103
104    Stats::Value simInsts;
105
106    Global();
107};
108
109Global::Global()
110{
111    simInsts
112        .functor(BaseCPU::numSimulatedInstructions)
113        .name("sim_insts")
114        .desc("Number of instructions simulated")
115        .precision(0)
116        .prereq(simInsts)
117        ;
118
119    simSeconds
120        .name("sim_seconds")
121        .desc("Number of seconds simulated")
122        ;
123
124    simFreq
125        .scalar(SimClock::Frequency)
126        .name("sim_freq")
127        .desc("Frequency of simulated ticks")
128        ;
129
130    simTicks
131        .functor(statElapsedTicks)
132        .name("sim_ticks")
133        .desc("Number of ticks simulated")
134        ;
135
136    finalTick
137        .functor(statFinalTick)
138        .name("final_tick")
139        .desc("Number of ticks from beginning of simulation \
140(restored from checkpoints and never reset)")
141        ;
142
143    hostInstRate
144        .name("host_inst_rate")
145        .desc("Simulator instruction rate (inst/s)")
146        .precision(0)
147        .prereq(simInsts)
148        ;
149
150    hostMemory
151        .functor(memUsage)
152        .name("host_mem_usage")
153        .desc("Number of bytes of host memory used")
154        .prereq(hostMemory)
155        ;
156
157    hostSeconds
158        .functor(statElapsedTime)
159        .name("host_seconds")
160        .desc("Real time elapsed on the host")
161        .precision(2)
162        ;
163
164    hostTickRate
165        .name("host_tick_rate")
166        .desc("Simulator tick rate (ticks/s)")
167        .precision(0)
168        ;
169
170    simSeconds = simTicks / simFreq;
171    hostInstRate = simInsts / hostSeconds;
172    hostTickRate = simTicks / hostSeconds;
173
174    registerResetCallback(&simTicksReset);
175}
176
177void
178initSimStats()
179{
180    static Global global;
181}
182
183class StatEvent : public Event
184{
185  private:
186    bool dump;
187    bool reset;
188    Tick repeat;
189
190  public:
191    StatEvent(bool _dump, bool _reset, Tick _repeat)
192        : Event(Stat_Event_Pri, AutoDelete),
193          dump(_dump), reset(_reset), repeat(_repeat)
194    {
195    }
196
197    virtual void
198    process()
199    {
200        if (dump)
201            Stats::dump();
202
203        if (reset)
204            Stats::reset();
205
206        if (repeat) {
207            Stats::schedStatEvent(dump, reset, curTick() + repeat, repeat);
208        }
209    }
210};
211
212void
213schedStatEvent(bool dump, bool reset, Tick when, Tick repeat)
214{
215    Event *event = new StatEvent(dump, reset, repeat);
216    mainEventQueue.schedule(event, when);
217}
218
219} // namespace Stats
220