stat_control.cc revision 5606
172SN/A/* 21762SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 372SN/A * All rights reserved. 472SN/A * 572SN/A * Redistribution and use in source and binary forms, with or without 672SN/A * modification, are permitted provided that the following conditions are 772SN/A * met: redistributions of source code must retain the above copyright 872SN/A * notice, this list of conditions and the following disclaimer; 972SN/A * redistributions in binary form must reproduce the above copyright 1072SN/A * notice, this list of conditions and the following disclaimer in the 1172SN/A * documentation and/or other materials provided with the distribution; 1272SN/A * neither the name of the copyright holders nor the names of its 1372SN/A * contributors may be used to endorse or promote products derived from 1472SN/A * this software without specific prior written permission. 1572SN/A * 1672SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1772SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1872SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1972SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2072SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2172SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2272SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2372SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2472SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2572SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2672SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Nathan Binkert 2972SN/A */ 3072SN/A 312SN/A// This file will contain default statistics for the simulator that 322SN/A// don't really belong to a specific simulator object 332SN/A 342SN/A#include <fstream> 352SN/A#include <iostream> 362SN/A#include <list> 372SN/A 382SN/A#include "base/callback.hh" 392SN/A#include "base/hostinfo.hh" 402SN/A#include "base/statistics.hh" 412SN/A#include "base/time.hh" 422SN/A#include "cpu/base.hh" 432SN/A#include "sim/eventq.hh" 442SN/A 452SN/Ausing namespace std; 462SN/A 472SN/AStats::Formula hostInstRate; 482SN/AStats::Formula hostTickRate; 492SN/AStats::Value hostMemory; 502SN/AStats::Value hostSeconds; 512SN/A 522SN/AStats::Value simTicks; 532SN/AStats::Value simInsts; 542SN/AStats::Value simFreq; 552SN/AStats::Formula simSeconds; 562SN/A 572SN/Anamespace Stats { 582SN/A 592SN/ATime statTime(true); 602SN/ATick startTick; 612SN/A 622SN/Astruct SimTicksReset : public Callback 632SN/A{ 642SN/A void process() 652SN/A { 662SN/A statTime.set(); 672SN/A startTick = curTick; 682SN/A } 692SN/A}; 702SN/A 712SN/Adouble 722SN/AstatElapsedTime() 732SN/A{ 742SN/A Time now(true); 752SN/A Time elapsed = now - statTime; 762SN/A return elapsed(); 772SN/A} 782SN/A 792SN/ATick 802SN/AstatElapsedTicks() 812SN/A{ 822SN/A return curTick - startTick; 832SN/A} 842SN/A 852SN/ASimTicksReset simTicksReset; 862SN/A 872SN/Avoid 882SN/AinitSimStats() 892SN/A{ 902SN/A simInsts 912SN/A .functor(BaseCPU::numSimulatedInstructions) 922SN/A .name("sim_insts") 932SN/A .desc("Number of instructions simulated") 942SN/A .precision(0) 952SN/A .prereq(simInsts) 962SN/A ; 972SN/A 982SN/A simSeconds 992SN/A .name("sim_seconds") 1002SN/A .desc("Number of seconds simulated") 1012SN/A ; 1022SN/A 1032SN/A simFreq 1042SN/A .scalar(Clock::Frequency) 1052SN/A .name("sim_freq") 1062SN/A .desc("Frequency of simulated ticks") 1072SN/A ; 1082SN/A 1092SN/A simTicks 1102SN/A .functor(statElapsedTicks) 1112SN/A .name("sim_ticks") 1122SN/A .desc("Number of ticks simulated") 1132SN/A ; 1142SN/A 1152SN/A hostInstRate 1162SN/A .name("host_inst_rate") 1172SN/A .desc("Simulator instruction rate (inst/s)") 1182SN/A .precision(0) 1192SN/A .prereq(simInsts) 1202SN/A ; 1211717SN/A 1222SN/A hostMemory 1232SN/A .functor(memUsage) 1242521SN/A .name("host_mem_usage") 12556SN/A .desc("Number of bytes of host memory used") 12656SN/A .prereq(hostMemory) 12756SN/A ; 12856SN/A 1292521SN/A hostSeconds 1302680Sktlim@umich.edu .functor(statElapsedTime) 1311717SN/A .name("host_seconds") 1322521SN/A .desc("Real time elapsed on the host") 1332521SN/A .precision(2) 1341717SN/A ; 1352SN/A 1362SN/A hostTickRate 1372107SN/A .name("host_tick_rate") 1382SN/A .desc("Simulator tick rate (ticks/s)") 1392009SN/A .precision(0) 1403536Sgblack@eecs.umich.edu ; 1412SN/A 1422SN/A simSeconds = simTicks / simFreq; 1432SN/A hostInstRate = simInsts / hostSeconds; 1442SN/A hostTickRate = simTicks / hostSeconds; 1453536Sgblack@eecs.umich.edu 1461910SN/A registerResetCallback(&simTicksReset); 1473536Sgblack@eecs.umich.edu} 1481910SN/A 1491910SN/Aclass _StatEvent : public Event 1501910SN/A{ 1513536Sgblack@eecs.umich.edu private: 1521910SN/A bool dump; 1532SN/A bool reset; 1542SN/A Tick repeat; 1552SN/A 1562SN/A public: 1572SN/A _StatEvent(bool _dump, bool _reset, Tick _repeat) 1582SN/A : Event(Stat_Event_Pri), dump(_dump), reset(_reset), repeat(_repeat) 1592SN/A { 1602SN/A setFlags(AutoDelete); 1612SN/A } 1622SN/A 1632SN/A virtual void 1642SN/A process() 1652SN/A { 1662SN/A if (dump) 1672SN/A Stats::dump(); 1682SN/A 1692SN/A if (reset) 1702SN/A Stats::reset(); 1713536Sgblack@eecs.umich.edu 1722SN/A if (repeat) { 1731910SN/A Event *event = new _StatEvent(dump, reset, repeat); 1741910SN/A mainEventQueue.schedule(event, curTick + repeat); 1751910SN/A } 1761910SN/A } 1772SN/A}; 1782SN/A 1792SN/Avoid 1802SN/AStatEvent(bool dump, bool reset, Tick when, Tick repeat) 1812SN/A{ 1822SN/A Event *event = new _StatEvent(dump, reset, repeat); 1832SN/A mainEventQueue.schedule(event, when); 184507SN/A} 185507SN/A 186507SN/A/* namespace Stats */ } 187507SN/A