sim_object.cc revision 7532
12SN/A/* 21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Nathan Binkert 302SN/A */ 312SN/A 326216Snate@binkert.org#include <cassert> 332SN/A 34330SN/A#include "base/callback.hh" 3556SN/A#include "base/inifile.hh" 361031SN/A#include "base/match.hh" 37330SN/A#include "base/misc.hh" 38330SN/A#include "base/trace.hh" 396214Snate@binkert.org#include "base/types.hh" 40330SN/A#include "sim/sim_object.hh" 41695SN/A#include "sim/stats.hh" 422SN/A 432SN/Ausing namespace std; 442SN/A 452SN/A 462SN/A//////////////////////////////////////////////////////////////////////// 472SN/A// 482SN/A// SimObject member definitions 492SN/A// 502SN/A//////////////////////////////////////////////////////////////////////// 512SN/A 522SN/A// 532SN/A// static list of all SimObjects, used for initialization etc. 542SN/A// 552SN/ASimObject::SimObjectList SimObject::simObjectList; 562SN/A 572SN/A// 582SN/A// SimObject constructor: used to maintain static simObjectList 592SN/A// 604762Snate@binkert.orgSimObject::SimObject(const Params *p) 615605Snate@binkert.org : EventManager(p->eventq), _params(p) 622SN/A{ 631031SN/A#ifdef DEBUG 641031SN/A doDebugBreak = false; 651031SN/A#endif 661031SN/A 671553SN/A simObjectList.push_back(this); 682901Ssaidi@eecs.umich.edu state = Running; 691553SN/A} 701553SN/A 71465SN/Avoid 72465SN/ASimObject::init() 73465SN/A{ 74465SN/A} 75465SN/A 767492Ssteve.reinhardt@amd.comvoid 777532Ssteve.reinhardt@amd.comSimObject::loadState(Checkpoint *cp) 787532Ssteve.reinhardt@amd.com{ 797532Ssteve.reinhardt@amd.com if (cp->sectionExists(name())) 807532Ssteve.reinhardt@amd.com unserialize(cp, name()); 817532Ssteve.reinhardt@amd.com} 827532Ssteve.reinhardt@amd.com 837532Ssteve.reinhardt@amd.comvoid 847532Ssteve.reinhardt@amd.comSimObject::initState() 857532Ssteve.reinhardt@amd.com{ 867532Ssteve.reinhardt@amd.com} 877532Ssteve.reinhardt@amd.com 887532Ssteve.reinhardt@amd.comvoid 897492Ssteve.reinhardt@amd.comSimObject::startup() 907492Ssteve.reinhardt@amd.com{ 917492Ssteve.reinhardt@amd.com} 927492Ssteve.reinhardt@amd.com 932SN/A// 942SN/A// no default statistics, so nothing to do in base implementation 952SN/A// 962SN/Avoid 972SN/ASimObject::regStats() 982SN/A{ 992SN/A} 1002SN/A 1012SN/Avoid 1022SN/ASimObject::regFormulas() 1032SN/A{ 1042SN/A} 1052SN/A 106330SN/Avoid 107330SN/ASimObject::resetStats() 108330SN/A{ 109330SN/A} 110330SN/A 1112SN/A// 112395SN/A// static function: serialize all SimObjects. 113395SN/A// 114395SN/Avoid 115395SN/ASimObject::serializeAll(ostream &os) 116395SN/A{ 117573SN/A SimObjectList::reverse_iterator ri = simObjectList.rbegin(); 118573SN/A SimObjectList::reverse_iterator rend = simObjectList.rend(); 119395SN/A 120573SN/A for (; ri != rend; ++ri) { 121573SN/A SimObject *obj = *ri; 122395SN/A obj->nameOut(os); 123395SN/A obj->serialize(os); 124395SN/A } 125395SN/A} 126843SN/A 1272797Sktlim@umich.eduvoid 1282797Sktlim@umich.eduSimObject::unserializeAll(Checkpoint *cp) 1292797Sktlim@umich.edu{ 1302797Sktlim@umich.edu SimObjectList::reverse_iterator ri = simObjectList.rbegin(); 1312797Sktlim@umich.edu SimObjectList::reverse_iterator rend = simObjectList.rend(); 1322797Sktlim@umich.edu 1332797Sktlim@umich.edu for (; ri != rend; ++ri) { 1342797Sktlim@umich.edu SimObject *obj = *ri; 1352797Sktlim@umich.edu DPRINTFR(Config, "Unserializing '%s'\n", 1362797Sktlim@umich.edu obj->name()); 1372797Sktlim@umich.edu if(cp->sectionExists(obj->name())) 1382797Sktlim@umich.edu obj->unserialize(cp, obj->name()); 1392797Sktlim@umich.edu else 1402797Sktlim@umich.edu warn("Not unserializing '%s': no section found in checkpoint.\n", 1412797Sktlim@umich.edu obj->name()); 1422797Sktlim@umich.edu } 1432797Sktlim@umich.edu} 1442797Sktlim@umich.edu 1457492Ssteve.reinhardt@amd.com 1467492Ssteve.reinhardt@amd.com 1471031SN/A#ifdef DEBUG 1481031SN/A// 1491031SN/A// static function: flag which objects should have the debugger break 1501031SN/A// 1511031SN/Avoid 1521031SN/ASimObject::debugObjectBreak(const string &objs) 1531031SN/A{ 1541031SN/A SimObjectList::const_iterator i = simObjectList.begin(); 1551031SN/A SimObjectList::const_iterator end = simObjectList.end(); 1561031SN/A 1571031SN/A ObjectMatch match(objs); 1581031SN/A for (; i != end; ++i) { 1591031SN/A SimObject *obj = *i; 1601031SN/A obj->doDebugBreak = match.match(obj->name()); 1611031SN/A } 1621031SN/A} 1631031SN/A 1641031SN/Avoid 1651031SN/AdebugObjectBreak(const char *objs) 1661031SN/A{ 1671031SN/A SimObject::debugObjectBreak(string(objs)); 1681031SN/A} 1691031SN/A#endif 1701031SN/A 1712901Ssaidi@eecs.umich.eduunsigned int 1722839Sktlim@umich.eduSimObject::drain(Event *drain_event) 1732797Sktlim@umich.edu{ 1742901Ssaidi@eecs.umich.edu state = Drained; 1752901Ssaidi@eecs.umich.edu return 0; 1762797Sktlim@umich.edu} 1772797Sktlim@umich.edu 1782609SN/Avoid 1792797Sktlim@umich.eduSimObject::resume() 1802609SN/A{ 1812901Ssaidi@eecs.umich.edu state = Running; 1822797Sktlim@umich.edu} 1832797Sktlim@umich.edu 1842797Sktlim@umich.eduvoid 1852797Sktlim@umich.eduSimObject::setMemoryMode(State new_mode) 1862797Sktlim@umich.edu{ 1872901Ssaidi@eecs.umich.edu panic("setMemoryMode() should only be called on systems"); 1882797Sktlim@umich.edu} 1892797Sktlim@umich.edu 1902797Sktlim@umich.eduvoid 1912797Sktlim@umich.eduSimObject::switchOut() 1922797Sktlim@umich.edu{ 1932797Sktlim@umich.edu panic("Unimplemented!"); 1942797Sktlim@umich.edu} 1952797Sktlim@umich.edu 1962797Sktlim@umich.eduvoid 1972797Sktlim@umich.eduSimObject::takeOverFrom(BaseCPU *cpu) 1982797Sktlim@umich.edu{ 1992797Sktlim@umich.edu panic("Unimplemented!"); 2002609SN/A} 2015314Sstever@gmail.com 2025314Sstever@gmail.com 2035314Sstever@gmail.comSimObject * 2045314Sstever@gmail.comSimObject::find(const char *name) 2055314Sstever@gmail.com{ 2065314Sstever@gmail.com SimObjectList::const_iterator i = simObjectList.begin(); 2075314Sstever@gmail.com SimObjectList::const_iterator end = simObjectList.end(); 2085314Sstever@gmail.com 2095314Sstever@gmail.com for (; i != end; ++i) { 2105314Sstever@gmail.com SimObject *obj = *i; 2115314Sstever@gmail.com if (obj->name() == name) 2125314Sstever@gmail.com return obj; 2135314Sstever@gmail.com } 2145314Sstever@gmail.com 2155314Sstever@gmail.com return NULL; 2165314Sstever@gmail.com} 217