sim_object.cc revision 7492
12SN/A/* 21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Nathan Binkert 302SN/A */ 312SN/A 326216Snate@binkert.org#include <cassert> 332SN/A 34330SN/A#include "base/callback.hh" 3556SN/A#include "base/inifile.hh" 361031SN/A#include "base/match.hh" 37330SN/A#include "base/misc.hh" 38330SN/A#include "base/trace.hh" 396214Snate@binkert.org#include "base/types.hh" 40330SN/A#include "sim/sim_object.hh" 41695SN/A#include "sim/stats.hh" 422SN/A 432SN/Ausing namespace std; 442SN/A 452SN/A 462SN/A//////////////////////////////////////////////////////////////////////// 472SN/A// 482SN/A// SimObject member definitions 492SN/A// 502SN/A//////////////////////////////////////////////////////////////////////// 512SN/A 522SN/A// 532SN/A// static list of all SimObjects, used for initialization etc. 542SN/A// 552SN/ASimObject::SimObjectList SimObject::simObjectList; 562SN/A 572SN/A// 582SN/A// SimObject constructor: used to maintain static simObjectList 592SN/A// 604762Snate@binkert.orgSimObject::SimObject(const Params *p) 615605Snate@binkert.org : EventManager(p->eventq), _params(p) 622SN/A{ 631031SN/A#ifdef DEBUG 641031SN/A doDebugBreak = false; 651031SN/A#endif 661031SN/A 671553SN/A simObjectList.push_back(this); 682901Ssaidi@eecs.umich.edu state = Running; 691553SN/A} 701553SN/A 71465SN/Avoid 72465SN/ASimObject::init() 73465SN/A{ 74465SN/A} 75465SN/A 767492Ssteve.reinhardt@amd.comvoid 777492Ssteve.reinhardt@amd.comSimObject::startup() 787492Ssteve.reinhardt@amd.com{ 797492Ssteve.reinhardt@amd.com} 807492Ssteve.reinhardt@amd.com 812SN/A// 822SN/A// no default statistics, so nothing to do in base implementation 832SN/A// 842SN/Avoid 852SN/ASimObject::regStats() 862SN/A{ 872SN/A} 882SN/A 892SN/Avoid 902SN/ASimObject::regFormulas() 912SN/A{ 922SN/A} 932SN/A 94330SN/Avoid 95330SN/ASimObject::resetStats() 96330SN/A{ 97330SN/A} 98330SN/A 992SN/A// 10053SN/A// static function: 10153SN/A// call regStats() on all SimObjects and then regFormulas() on all 10253SN/A// SimObjects. 1032SN/A// 104334SN/Astruct SimObjectResetCB : public Callback 105334SN/A{ 106334SN/A virtual void process() { SimObject::resetAllStats(); } 107334SN/A}; 108334SN/A 109334SN/Anamespace { 110334SN/A static SimObjectResetCB StatResetCB; 111334SN/A} 112334SN/A 1132SN/Avoid 1142SN/ASimObject::regAllStats() 1152SN/A{ 1162SN/A SimObjectList::iterator i; 1172SN/A SimObjectList::iterator end = simObjectList.end(); 1182SN/A 1192SN/A /** 1202SN/A * @todo change cprintfs to DPRINTFs 1212SN/A */ 1222SN/A for (i = simObjectList.begin(); i != end; ++i) { 1232SN/A#ifdef STAT_DEBUG 1242SN/A cprintf("registering stats for %s\n", (*i)->name()); 1252SN/A#endif 1262SN/A (*i)->regStats(); 1272SN/A } 1282SN/A 1292SN/A for (i = simObjectList.begin(); i != end; ++i) { 1302SN/A#ifdef STAT_DEBUG 1312SN/A cprintf("registering formulas for %s\n", (*i)->name()); 1322SN/A#endif 1332SN/A (*i)->regFormulas(); 134334SN/A } 135334SN/A 136729SN/A Stats::registerResetCallback(&StatResetCB); 1372SN/A} 1382SN/A 1392SN/A// 140465SN/A// static function: call init() on all SimObjects. 141465SN/A// 142465SN/Avoid 143465SN/ASimObject::initAll() 144465SN/A{ 145465SN/A SimObjectList::iterator i = simObjectList.begin(); 146465SN/A SimObjectList::iterator end = simObjectList.end(); 147465SN/A 148465SN/A for (; i != end; ++i) { 149465SN/A SimObject *obj = *i; 150465SN/A obj->init(); 151465SN/A } 152465SN/A} 153465SN/A 154465SN/A// 155330SN/A// static function: call resetStats() on all SimObjects. 156330SN/A// 157330SN/Avoid 158330SN/ASimObject::resetAllStats() 159330SN/A{ 160332SN/A SimObjectList::iterator i = simObjectList.begin(); 161332SN/A SimObjectList::iterator end = simObjectList.end(); 162332SN/A 163332SN/A for (; i != end; ++i) { 164332SN/A SimObject *obj = *i; 165332SN/A obj->resetStats(); 166332SN/A } 167330SN/A} 168330SN/A 169330SN/A// 170395SN/A// static function: serialize all SimObjects. 171395SN/A// 172395SN/Avoid 173395SN/ASimObject::serializeAll(ostream &os) 174395SN/A{ 175573SN/A SimObjectList::reverse_iterator ri = simObjectList.rbegin(); 176573SN/A SimObjectList::reverse_iterator rend = simObjectList.rend(); 177395SN/A 178573SN/A for (; ri != rend; ++ri) { 179573SN/A SimObject *obj = *ri; 180395SN/A obj->nameOut(os); 181395SN/A obj->serialize(os); 182395SN/A } 183395SN/A} 184843SN/A 1852797Sktlim@umich.eduvoid 1862797Sktlim@umich.eduSimObject::unserializeAll(Checkpoint *cp) 1872797Sktlim@umich.edu{ 1882797Sktlim@umich.edu SimObjectList::reverse_iterator ri = simObjectList.rbegin(); 1892797Sktlim@umich.edu SimObjectList::reverse_iterator rend = simObjectList.rend(); 1902797Sktlim@umich.edu 1912797Sktlim@umich.edu for (; ri != rend; ++ri) { 1922797Sktlim@umich.edu SimObject *obj = *ri; 1932797Sktlim@umich.edu DPRINTFR(Config, "Unserializing '%s'\n", 1942797Sktlim@umich.edu obj->name()); 1952797Sktlim@umich.edu if(cp->sectionExists(obj->name())) 1962797Sktlim@umich.edu obj->unserialize(cp, obj->name()); 1972797Sktlim@umich.edu else 1982797Sktlim@umich.edu warn("Not unserializing '%s': no section found in checkpoint.\n", 1992797Sktlim@umich.edu obj->name()); 2002797Sktlim@umich.edu } 2012797Sktlim@umich.edu} 2022797Sktlim@umich.edu 2037492Ssteve.reinhardt@amd.com 2047492Ssteve.reinhardt@amd.comvoid 2057492Ssteve.reinhardt@amd.comSimObject::startupAll() 2067492Ssteve.reinhardt@amd.com{ 2077492Ssteve.reinhardt@amd.com SimObjectList::iterator i = simObjectList.begin(); 2087492Ssteve.reinhardt@amd.com SimObjectList::iterator end = simObjectList.end(); 2097492Ssteve.reinhardt@amd.com 2107492Ssteve.reinhardt@amd.com while (i != end) { 2117492Ssteve.reinhardt@amd.com (*i)->startup(); 2127492Ssteve.reinhardt@amd.com ++i; 2137492Ssteve.reinhardt@amd.com } 2147492Ssteve.reinhardt@amd.com} 2157492Ssteve.reinhardt@amd.com 2167492Ssteve.reinhardt@amd.com 2171031SN/A#ifdef DEBUG 2181031SN/A// 2191031SN/A// static function: flag which objects should have the debugger break 2201031SN/A// 2211031SN/Avoid 2221031SN/ASimObject::debugObjectBreak(const string &objs) 2231031SN/A{ 2241031SN/A SimObjectList::const_iterator i = simObjectList.begin(); 2251031SN/A SimObjectList::const_iterator end = simObjectList.end(); 2261031SN/A 2271031SN/A ObjectMatch match(objs); 2281031SN/A for (; i != end; ++i) { 2291031SN/A SimObject *obj = *i; 2301031SN/A obj->doDebugBreak = match.match(obj->name()); 2311031SN/A } 2321031SN/A} 2331031SN/A 2341031SN/Avoid 2351031SN/AdebugObjectBreak(const char *objs) 2361031SN/A{ 2371031SN/A SimObject::debugObjectBreak(string(objs)); 2381031SN/A} 2391031SN/A#endif 2401031SN/A 2412901Ssaidi@eecs.umich.eduunsigned int 2422839Sktlim@umich.eduSimObject::drain(Event *drain_event) 2432797Sktlim@umich.edu{ 2442901Ssaidi@eecs.umich.edu state = Drained; 2452901Ssaidi@eecs.umich.edu return 0; 2462797Sktlim@umich.edu} 2472797Sktlim@umich.edu 2482609SN/Avoid 2492797Sktlim@umich.eduSimObject::resume() 2502609SN/A{ 2512901Ssaidi@eecs.umich.edu state = Running; 2522797Sktlim@umich.edu} 2532797Sktlim@umich.edu 2542797Sktlim@umich.eduvoid 2552797Sktlim@umich.eduSimObject::setMemoryMode(State new_mode) 2562797Sktlim@umich.edu{ 2572901Ssaidi@eecs.umich.edu panic("setMemoryMode() should only be called on systems"); 2582797Sktlim@umich.edu} 2592797Sktlim@umich.edu 2602797Sktlim@umich.eduvoid 2612797Sktlim@umich.eduSimObject::switchOut() 2622797Sktlim@umich.edu{ 2632797Sktlim@umich.edu panic("Unimplemented!"); 2642797Sktlim@umich.edu} 2652797Sktlim@umich.edu 2662797Sktlim@umich.eduvoid 2672797Sktlim@umich.eduSimObject::takeOverFrom(BaseCPU *cpu) 2682797Sktlim@umich.edu{ 2692797Sktlim@umich.edu panic("Unimplemented!"); 2702609SN/A} 2715314Sstever@gmail.com 2725314Sstever@gmail.com 2735314Sstever@gmail.comSimObject * 2745314Sstever@gmail.comSimObject::find(const char *name) 2755314Sstever@gmail.com{ 2765314Sstever@gmail.com SimObjectList::const_iterator i = simObjectList.begin(); 2775314Sstever@gmail.com SimObjectList::const_iterator end = simObjectList.end(); 2785314Sstever@gmail.com 2795314Sstever@gmail.com for (; i != end; ++i) { 2805314Sstever@gmail.com SimObject *obj = *i; 2815314Sstever@gmail.com if (obj->name() == name) 2825314Sstever@gmail.com return obj; 2835314Sstever@gmail.com } 2845314Sstever@gmail.com 2855314Sstever@gmail.com return NULL; 2865314Sstever@gmail.com} 287