sim_object.cc revision 6214
12SN/A/*
21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan
32SN/A * All rights reserved.
42SN/A *
52SN/A * Redistribution and use in source and binary forms, with or without
62SN/A * modification, are permitted provided that the following conditions are
72SN/A * met: redistributions of source code must retain the above copyright
82SN/A * notice, this list of conditions and the following disclaimer;
92SN/A * redistributions in binary form must reproduce the above copyright
102SN/A * notice, this list of conditions and the following disclaimer in the
112SN/A * documentation and/or other materials provided with the distribution;
122SN/A * neither the name of the copyright holders nor the names of its
132SN/A * contributors may be used to endorse or promote products derived from
142SN/A * this software without specific prior written permission.
152SN/A *
162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt
292665Ssaidi@eecs.umich.edu *          Nathan Binkert
302SN/A */
312SN/A
322SN/A#include <assert.h>
332SN/A
34330SN/A#include "base/callback.hh"
3556SN/A#include "base/inifile.hh"
361031SN/A#include "base/match.hh"
37330SN/A#include "base/misc.hh"
38330SN/A#include "base/trace.hh"
39938SN/A#include "base/stats/events.hh"
406214Snate@binkert.org#include "base/types.hh"
41330SN/A#include "sim/sim_object.hh"
42695SN/A#include "sim/stats.hh"
432SN/A
442SN/Ausing namespace std;
452SN/A
462SN/A
472SN/A////////////////////////////////////////////////////////////////////////
482SN/A//
492SN/A// SimObject member definitions
502SN/A//
512SN/A////////////////////////////////////////////////////////////////////////
522SN/A
532SN/A//
542SN/A// static list of all SimObjects, used for initialization etc.
552SN/A//
562SN/ASimObject::SimObjectList SimObject::simObjectList;
572SN/A
582SN/A//
592SN/A// SimObject constructor: used to maintain static simObjectList
602SN/A//
614762Snate@binkert.orgSimObject::SimObject(const Params *p)
625605Snate@binkert.org    : EventManager(p->eventq), _params(p)
632SN/A{
641031SN/A#ifdef DEBUG
651031SN/A    doDebugBreak = false;
661031SN/A#endif
671031SN/A
681553SN/A    simObjectList.push_back(this);
692901Ssaidi@eecs.umich.edu    state = Running;
701553SN/A}
711553SN/A
72465SN/Avoid
73465SN/ASimObject::init()
74465SN/A{
75465SN/A}
76465SN/A
772SN/A//
782SN/A// no default statistics, so nothing to do in base implementation
792SN/A//
802SN/Avoid
812SN/ASimObject::regStats()
822SN/A{
832SN/A}
842SN/A
852SN/Avoid
862SN/ASimObject::regFormulas()
872SN/A{
882SN/A}
892SN/A
90330SN/Avoid
91330SN/ASimObject::resetStats()
92330SN/A{
93330SN/A}
94330SN/A
952SN/A//
9653SN/A// static function:
9753SN/A//   call regStats() on all SimObjects and then regFormulas() on all
9853SN/A//   SimObjects.
992SN/A//
100334SN/Astruct SimObjectResetCB : public Callback
101334SN/A{
102334SN/A    virtual void process() { SimObject::resetAllStats(); }
103334SN/A};
104334SN/A
105334SN/Anamespace {
106334SN/A    static SimObjectResetCB StatResetCB;
107334SN/A}
108334SN/A
1092SN/Avoid
1102SN/ASimObject::regAllStats()
1112SN/A{
1122SN/A    SimObjectList::iterator i;
1132SN/A    SimObjectList::iterator end = simObjectList.end();
1142SN/A
1152SN/A    /**
1162SN/A     * @todo change cprintfs to DPRINTFs
1172SN/A     */
1182SN/A    for (i = simObjectList.begin(); i != end; ++i) {
1192SN/A#ifdef STAT_DEBUG
1202SN/A        cprintf("registering stats for %s\n", (*i)->name());
1212SN/A#endif
1222SN/A        (*i)->regStats();
1232SN/A    }
1242SN/A
1252SN/A    for (i = simObjectList.begin(); i != end; ++i) {
1262SN/A#ifdef STAT_DEBUG
1272SN/A        cprintf("registering formulas for %s\n", (*i)->name());
1282SN/A#endif
1292SN/A        (*i)->regFormulas();
130334SN/A    }
131334SN/A
132729SN/A    Stats::registerResetCallback(&StatResetCB);
1332SN/A}
1342SN/A
1352SN/A//
136465SN/A// static function: call init() on all SimObjects.
137465SN/A//
138465SN/Avoid
139465SN/ASimObject::initAll()
140465SN/A{
141465SN/A    SimObjectList::iterator i = simObjectList.begin();
142465SN/A    SimObjectList::iterator end = simObjectList.end();
143465SN/A
144465SN/A    for (; i != end; ++i) {
145465SN/A        SimObject *obj = *i;
146465SN/A        obj->init();
147465SN/A    }
148465SN/A}
149465SN/A
150465SN/A//
151330SN/A// static function: call resetStats() on all SimObjects.
152330SN/A//
153330SN/Avoid
154330SN/ASimObject::resetAllStats()
155330SN/A{
156332SN/A    SimObjectList::iterator i = simObjectList.begin();
157332SN/A    SimObjectList::iterator end = simObjectList.end();
158332SN/A
159332SN/A    for (; i != end; ++i) {
160332SN/A        SimObject *obj = *i;
161332SN/A        obj->resetStats();
162332SN/A    }
163330SN/A}
164330SN/A
165330SN/A//
166395SN/A// static function: serialize all SimObjects.
167395SN/A//
168395SN/Avoid
169395SN/ASimObject::serializeAll(ostream &os)
170395SN/A{
171573SN/A    SimObjectList::reverse_iterator ri = simObjectList.rbegin();
172573SN/A    SimObjectList::reverse_iterator rend = simObjectList.rend();
173395SN/A
174573SN/A    for (; ri != rend; ++ri) {
175573SN/A        SimObject *obj = *ri;
176395SN/A        obj->nameOut(os);
177395SN/A        obj->serialize(os);
178395SN/A   }
179395SN/A}
180843SN/A
1812797Sktlim@umich.eduvoid
1822797Sktlim@umich.eduSimObject::unserializeAll(Checkpoint *cp)
1832797Sktlim@umich.edu{
1842797Sktlim@umich.edu    SimObjectList::reverse_iterator ri = simObjectList.rbegin();
1852797Sktlim@umich.edu    SimObjectList::reverse_iterator rend = simObjectList.rend();
1862797Sktlim@umich.edu
1872797Sktlim@umich.edu    for (; ri != rend; ++ri) {
1882797Sktlim@umich.edu        SimObject *obj = *ri;
1892797Sktlim@umich.edu        DPRINTFR(Config, "Unserializing '%s'\n",
1902797Sktlim@umich.edu                 obj->name());
1912797Sktlim@umich.edu        if(cp->sectionExists(obj->name()))
1922797Sktlim@umich.edu            obj->unserialize(cp, obj->name());
1932797Sktlim@umich.edu        else
1942797Sktlim@umich.edu            warn("Not unserializing '%s': no section found in checkpoint.\n",
1952797Sktlim@umich.edu                 obj->name());
1962797Sktlim@umich.edu   }
1972797Sktlim@umich.edu}
1982797Sktlim@umich.edu
1991031SN/A#ifdef DEBUG
2001031SN/A//
2011031SN/A// static function: flag which objects should have the debugger break
2021031SN/A//
2031031SN/Avoid
2041031SN/ASimObject::debugObjectBreak(const string &objs)
2051031SN/A{
2061031SN/A    SimObjectList::const_iterator i = simObjectList.begin();
2071031SN/A    SimObjectList::const_iterator end = simObjectList.end();
2081031SN/A
2091031SN/A    ObjectMatch match(objs);
2101031SN/A    for (; i != end; ++i) {
2111031SN/A        SimObject *obj = *i;
2121031SN/A        obj->doDebugBreak = match.match(obj->name());
2131031SN/A   }
2141031SN/A}
2151031SN/A
2161031SN/Avoid
2171031SN/AdebugObjectBreak(const char *objs)
2181031SN/A{
2191031SN/A    SimObject::debugObjectBreak(string(objs));
2201031SN/A}
2211031SN/A#endif
2221031SN/A
223938SN/Avoid
224938SN/ASimObject::recordEvent(const std::string &stat)
225938SN/A{
2264076Sbinkertn@umich.edu    Stats::recordEvent(stat);
227938SN/A}
228938SN/A
2292901Ssaidi@eecs.umich.eduunsigned int
2302839Sktlim@umich.eduSimObject::drain(Event *drain_event)
2312797Sktlim@umich.edu{
2322901Ssaidi@eecs.umich.edu    state = Drained;
2332901Ssaidi@eecs.umich.edu    return 0;
2342797Sktlim@umich.edu}
2352797Sktlim@umich.edu
2362609SN/Avoid
2372797Sktlim@umich.eduSimObject::resume()
2382609SN/A{
2392901Ssaidi@eecs.umich.edu    state = Running;
2402797Sktlim@umich.edu}
2412797Sktlim@umich.edu
2422797Sktlim@umich.eduvoid
2432797Sktlim@umich.eduSimObject::setMemoryMode(State new_mode)
2442797Sktlim@umich.edu{
2452901Ssaidi@eecs.umich.edu    panic("setMemoryMode() should only be called on systems");
2462797Sktlim@umich.edu}
2472797Sktlim@umich.edu
2482797Sktlim@umich.eduvoid
2492797Sktlim@umich.eduSimObject::switchOut()
2502797Sktlim@umich.edu{
2512797Sktlim@umich.edu    panic("Unimplemented!");
2522797Sktlim@umich.edu}
2532797Sktlim@umich.edu
2542797Sktlim@umich.eduvoid
2552797Sktlim@umich.eduSimObject::takeOverFrom(BaseCPU *cpu)
2562797Sktlim@umich.edu{
2572797Sktlim@umich.edu    panic("Unimplemented!");
2582609SN/A}
2595314Sstever@gmail.com
2605314Sstever@gmail.com
2615314Sstever@gmail.comSimObject *
2625314Sstever@gmail.comSimObject::find(const char *name)
2635314Sstever@gmail.com{
2645314Sstever@gmail.com    SimObjectList::const_iterator i = simObjectList.begin();
2655314Sstever@gmail.com    SimObjectList::const_iterator end = simObjectList.end();
2665314Sstever@gmail.com
2675314Sstever@gmail.com    for (; i != end; ++i) {
2685314Sstever@gmail.com        SimObject *obj = *i;
2695314Sstever@gmail.com        if (obj->name() == name)
2705314Sstever@gmail.com            return obj;
2715314Sstever@gmail.com    }
2725314Sstever@gmail.com
2735314Sstever@gmail.com    return NULL;
2745314Sstever@gmail.com}
275