sim_object.cc revision 5314
12SN/A/*
21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan
32SN/A * All rights reserved.
42SN/A *
52SN/A * Redistribution and use in source and binary forms, with or without
62SN/A * modification, are permitted provided that the following conditions are
72SN/A * met: redistributions of source code must retain the above copyright
82SN/A * notice, this list of conditions and the following disclaimer;
92SN/A * redistributions in binary form must reproduce the above copyright
102SN/A * notice, this list of conditions and the following disclaimer in the
112SN/A * documentation and/or other materials provided with the distribution;
122SN/A * neither the name of the copyright holders nor the names of its
132SN/A * contributors may be used to endorse or promote products derived from
142SN/A * this software without specific prior written permission.
152SN/A *
162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt
292665Ssaidi@eecs.umich.edu *          Nathan Binkert
302SN/A */
312SN/A
322SN/A#include <assert.h>
332SN/A
34330SN/A#include "base/callback.hh"
3556SN/A#include "base/inifile.hh"
361031SN/A#include "base/match.hh"
37330SN/A#include "base/misc.hh"
38330SN/A#include "base/trace.hh"
39938SN/A#include "base/stats/events.hh"
4056SN/A#include "sim/host.hh"
41330SN/A#include "sim/sim_object.hh"
42695SN/A#include "sim/stats.hh"
432SN/A
442SN/Ausing namespace std;
452SN/A
462SN/A
472SN/A////////////////////////////////////////////////////////////////////////
482SN/A//
492SN/A// SimObject member definitions
502SN/A//
512SN/A////////////////////////////////////////////////////////////////////////
522SN/A
532SN/A//
542SN/A// static list of all SimObjects, used for initialization etc.
552SN/A//
562SN/ASimObject::SimObjectList SimObject::simObjectList;
572SN/A
582SN/A//
592SN/A// SimObject constructor: used to maintain static simObjectList
602SN/A//
614762Snate@binkert.orgSimObject::SimObject(const Params *p)
621553SN/A    : _params(p)
632SN/A{
641031SN/A#ifdef DEBUG
651031SN/A    doDebugBreak = false;
661031SN/A#endif
671031SN/A
681553SN/A    simObjectList.push_back(this);
692901Ssaidi@eecs.umich.edu    state = Running;
701553SN/A}
711553SN/A
724762Snate@binkert.orgSimObjectParams *
735034Smilesck@eecs.umich.eduSimObject::makeParams(const std::string &name)
744762Snate@binkert.org{
754762Snate@binkert.org    SimObjectParams *params = new SimObjectParams;
764762Snate@binkert.org    params->name = name;
774762Snate@binkert.org    return params;
784762Snate@binkert.org}
794762Snate@binkert.org
80465SN/Avoid
81465SN/ASimObject::init()
82465SN/A{
83465SN/A}
84465SN/A
852SN/A//
862SN/A// no default statistics, so nothing to do in base implementation
872SN/A//
882SN/Avoid
892SN/ASimObject::regStats()
902SN/A{
912SN/A}
922SN/A
932SN/Avoid
942SN/ASimObject::regFormulas()
952SN/A{
962SN/A}
972SN/A
98330SN/Avoid
99330SN/ASimObject::resetStats()
100330SN/A{
101330SN/A}
102330SN/A
1032SN/A//
10453SN/A// static function:
10553SN/A//   call regStats() on all SimObjects and then regFormulas() on all
10653SN/A//   SimObjects.
1072SN/A//
108334SN/Astruct SimObjectResetCB : public Callback
109334SN/A{
110334SN/A    virtual void process() { SimObject::resetAllStats(); }
111334SN/A};
112334SN/A
113334SN/Anamespace {
114334SN/A    static SimObjectResetCB StatResetCB;
115334SN/A}
116334SN/A
1172SN/Avoid
1182SN/ASimObject::regAllStats()
1192SN/A{
1202SN/A    SimObjectList::iterator i;
1212SN/A    SimObjectList::iterator end = simObjectList.end();
1222SN/A
1232SN/A    /**
1242SN/A     * @todo change cprintfs to DPRINTFs
1252SN/A     */
1262SN/A    for (i = simObjectList.begin(); i != end; ++i) {
1272SN/A#ifdef STAT_DEBUG
1282SN/A        cprintf("registering stats for %s\n", (*i)->name());
1292SN/A#endif
1302SN/A        (*i)->regStats();
1312SN/A    }
1322SN/A
1332SN/A    for (i = simObjectList.begin(); i != end; ++i) {
1342SN/A#ifdef STAT_DEBUG
1352SN/A        cprintf("registering formulas for %s\n", (*i)->name());
1362SN/A#endif
1372SN/A        (*i)->regFormulas();
138334SN/A    }
139334SN/A
140729SN/A    Stats::registerResetCallback(&StatResetCB);
1412SN/A}
1422SN/A
1432SN/A//
144465SN/A// static function: call init() on all SimObjects.
145465SN/A//
146465SN/Avoid
147465SN/ASimObject::initAll()
148465SN/A{
149465SN/A    SimObjectList::iterator i = simObjectList.begin();
150465SN/A    SimObjectList::iterator end = simObjectList.end();
151465SN/A
152465SN/A    for (; i != end; ++i) {
153465SN/A        SimObject *obj = *i;
154465SN/A        obj->init();
155465SN/A    }
156465SN/A}
157465SN/A
158465SN/A//
159330SN/A// static function: call resetStats() on all SimObjects.
160330SN/A//
161330SN/Avoid
162330SN/ASimObject::resetAllStats()
163330SN/A{
164332SN/A    SimObjectList::iterator i = simObjectList.begin();
165332SN/A    SimObjectList::iterator end = simObjectList.end();
166332SN/A
167332SN/A    for (; i != end; ++i) {
168332SN/A        SimObject *obj = *i;
169332SN/A        obj->resetStats();
170332SN/A    }
171330SN/A}
172330SN/A
173330SN/A//
174395SN/A// static function: serialize all SimObjects.
175395SN/A//
176395SN/Avoid
177395SN/ASimObject::serializeAll(ostream &os)
178395SN/A{
179573SN/A    SimObjectList::reverse_iterator ri = simObjectList.rbegin();
180573SN/A    SimObjectList::reverse_iterator rend = simObjectList.rend();
181395SN/A
182573SN/A    for (; ri != rend; ++ri) {
183573SN/A        SimObject *obj = *ri;
184395SN/A        obj->nameOut(os);
185395SN/A        obj->serialize(os);
186395SN/A   }
187395SN/A}
188843SN/A
1892797Sktlim@umich.eduvoid
1902797Sktlim@umich.eduSimObject::unserializeAll(Checkpoint *cp)
1912797Sktlim@umich.edu{
1922797Sktlim@umich.edu    SimObjectList::reverse_iterator ri = simObjectList.rbegin();
1932797Sktlim@umich.edu    SimObjectList::reverse_iterator rend = simObjectList.rend();
1942797Sktlim@umich.edu
1952797Sktlim@umich.edu    for (; ri != rend; ++ri) {
1962797Sktlim@umich.edu        SimObject *obj = *ri;
1972797Sktlim@umich.edu        DPRINTFR(Config, "Unserializing '%s'\n",
1982797Sktlim@umich.edu                 obj->name());
1992797Sktlim@umich.edu        if(cp->sectionExists(obj->name()))
2002797Sktlim@umich.edu            obj->unserialize(cp, obj->name());
2012797Sktlim@umich.edu        else
2022797Sktlim@umich.edu            warn("Not unserializing '%s': no section found in checkpoint.\n",
2032797Sktlim@umich.edu                 obj->name());
2042797Sktlim@umich.edu   }
2052797Sktlim@umich.edu}
2062797Sktlim@umich.edu
2071031SN/A#ifdef DEBUG
2081031SN/A//
2091031SN/A// static function: flag which objects should have the debugger break
2101031SN/A//
2111031SN/Avoid
2121031SN/ASimObject::debugObjectBreak(const string &objs)
2131031SN/A{
2141031SN/A    SimObjectList::const_iterator i = simObjectList.begin();
2151031SN/A    SimObjectList::const_iterator end = simObjectList.end();
2161031SN/A
2171031SN/A    ObjectMatch match(objs);
2181031SN/A    for (; i != end; ++i) {
2191031SN/A        SimObject *obj = *i;
2201031SN/A        obj->doDebugBreak = match.match(obj->name());
2211031SN/A   }
2221031SN/A}
2231031SN/A
2241031SN/Avoid
2251031SN/AdebugObjectBreak(const char *objs)
2261031SN/A{
2271031SN/A    SimObject::debugObjectBreak(string(objs));
2281031SN/A}
2291031SN/A#endif
2301031SN/A
231938SN/Avoid
232938SN/ASimObject::recordEvent(const std::string &stat)
233938SN/A{
2344076Sbinkertn@umich.edu    Stats::recordEvent(stat);
235938SN/A}
236938SN/A
2372901Ssaidi@eecs.umich.eduunsigned int
2382839Sktlim@umich.eduSimObject::drain(Event *drain_event)
2392797Sktlim@umich.edu{
2402901Ssaidi@eecs.umich.edu    state = Drained;
2412901Ssaidi@eecs.umich.edu    return 0;
2422797Sktlim@umich.edu}
2432797Sktlim@umich.edu
2442609SN/Avoid
2452797Sktlim@umich.eduSimObject::resume()
2462609SN/A{
2472901Ssaidi@eecs.umich.edu    state = Running;
2482797Sktlim@umich.edu}
2492797Sktlim@umich.edu
2502797Sktlim@umich.eduvoid
2512797Sktlim@umich.eduSimObject::setMemoryMode(State new_mode)
2522797Sktlim@umich.edu{
2532901Ssaidi@eecs.umich.edu    panic("setMemoryMode() should only be called on systems");
2542797Sktlim@umich.edu}
2552797Sktlim@umich.edu
2562797Sktlim@umich.eduvoid
2572797Sktlim@umich.eduSimObject::switchOut()
2582797Sktlim@umich.edu{
2592797Sktlim@umich.edu    panic("Unimplemented!");
2602797Sktlim@umich.edu}
2612797Sktlim@umich.edu
2622797Sktlim@umich.eduvoid
2632797Sktlim@umich.eduSimObject::takeOverFrom(BaseCPU *cpu)
2642797Sktlim@umich.edu{
2652797Sktlim@umich.edu    panic("Unimplemented!");
2662609SN/A}
2675314Sstever@gmail.com
2685314Sstever@gmail.com
2695314Sstever@gmail.comSimObject *
2705314Sstever@gmail.comSimObject::find(const char *name)
2715314Sstever@gmail.com{
2725314Sstever@gmail.com    SimObjectList::const_iterator i = simObjectList.begin();
2735314Sstever@gmail.com    SimObjectList::const_iterator end = simObjectList.end();
2745314Sstever@gmail.com
2755314Sstever@gmail.com    for (; i != end; ++i) {
2765314Sstever@gmail.com        SimObject *obj = *i;
2775314Sstever@gmail.com        if (obj->name() == name)
2785314Sstever@gmail.com            return obj;
2795314Sstever@gmail.com    }
2805314Sstever@gmail.com
2815314Sstever@gmail.com    return NULL;
2825314Sstever@gmail.com}
283