sim_object.cc revision 4076
12SN/A/* 21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Nathan Binkert 302SN/A */ 312SN/A 322SN/A#include <assert.h> 332SN/A 34330SN/A#include "base/callback.hh" 3556SN/A#include "base/inifile.hh" 361031SN/A#include "base/match.hh" 37330SN/A#include "base/misc.hh" 38330SN/A#include "base/trace.hh" 39938SN/A#include "base/stats/events.hh" 4056SN/A#include "sim/host.hh" 41330SN/A#include "sim/sim_object.hh" 42695SN/A#include "sim/stats.hh" 43843SN/A#include "sim/param.hh" 442SN/A 452SN/Ausing namespace std; 462SN/A 472SN/A 482SN/A//////////////////////////////////////////////////////////////////////// 492SN/A// 502SN/A// SimObject member definitions 512SN/A// 522SN/A//////////////////////////////////////////////////////////////////////// 532SN/A 542SN/A// 552SN/A// static list of all SimObjects, used for initialization etc. 562SN/A// 572SN/ASimObject::SimObjectList SimObject::simObjectList; 582SN/A 592SN/A// 602SN/A// SimObject constructor: used to maintain static simObjectList 612SN/A// 621553SN/ASimObject::SimObject(Params *p) 631553SN/A : _params(p) 642SN/A{ 651031SN/A#ifdef DEBUG 661031SN/A doDebugBreak = false; 671031SN/A#endif 681031SN/A 691553SN/A simObjectList.push_back(this); 702901Ssaidi@eecs.umich.edu state = Running; 711553SN/A} 721553SN/A 731553SN/A// 741553SN/A// SimObject constructor: used to maintain static simObjectList 751553SN/A// 761553SN/ASimObject::SimObject(const string &_name) 771553SN/A : _params(new Params) 781553SN/A{ 791553SN/A _params->name = _name; 801553SN/A#ifdef DEBUG 811553SN/A doDebugBreak = false; 821553SN/A#endif 831553SN/A 842SN/A simObjectList.push_back(this); 852901Ssaidi@eecs.umich.edu state = Running; 862SN/A} 872SN/A 88465SN/Avoid 89465SN/ASimObject::init() 90465SN/A{ 91465SN/A} 92465SN/A 932SN/A// 942SN/A// no default statistics, so nothing to do in base implementation 952SN/A// 962SN/Avoid 972SN/ASimObject::regStats() 982SN/A{ 992SN/A} 1002SN/A 1012SN/Avoid 1022SN/ASimObject::regFormulas() 1032SN/A{ 1042SN/A} 1052SN/A 106330SN/Avoid 107330SN/ASimObject::resetStats() 108330SN/A{ 109330SN/A} 110330SN/A 1112SN/A// 11253SN/A// static function: 11353SN/A// call regStats() on all SimObjects and then regFormulas() on all 11453SN/A// SimObjects. 1152SN/A// 116334SN/Astruct SimObjectResetCB : public Callback 117334SN/A{ 118334SN/A virtual void process() { SimObject::resetAllStats(); } 119334SN/A}; 120334SN/A 121334SN/Anamespace { 122334SN/A static SimObjectResetCB StatResetCB; 123334SN/A} 124334SN/A 1252SN/Avoid 1262SN/ASimObject::regAllStats() 1272SN/A{ 1282SN/A SimObjectList::iterator i; 1292SN/A SimObjectList::iterator end = simObjectList.end(); 1302SN/A 1312SN/A /** 1322SN/A * @todo change cprintfs to DPRINTFs 1332SN/A */ 1342SN/A for (i = simObjectList.begin(); i != end; ++i) { 1352SN/A#ifdef STAT_DEBUG 1362SN/A cprintf("registering stats for %s\n", (*i)->name()); 1372SN/A#endif 1382SN/A (*i)->regStats(); 1392SN/A } 1402SN/A 1412SN/A for (i = simObjectList.begin(); i != end; ++i) { 1422SN/A#ifdef STAT_DEBUG 1432SN/A cprintf("registering formulas for %s\n", (*i)->name()); 1442SN/A#endif 1452SN/A (*i)->regFormulas(); 146334SN/A } 147334SN/A 148729SN/A Stats::registerResetCallback(&StatResetCB); 1492SN/A} 1502SN/A 1512SN/A// 152465SN/A// static function: call init() on all SimObjects. 153465SN/A// 154465SN/Avoid 155465SN/ASimObject::initAll() 156465SN/A{ 157465SN/A SimObjectList::iterator i = simObjectList.begin(); 158465SN/A SimObjectList::iterator end = simObjectList.end(); 159465SN/A 160465SN/A for (; i != end; ++i) { 161465SN/A SimObject *obj = *i; 162465SN/A obj->init(); 163465SN/A } 164465SN/A} 165465SN/A 166465SN/A// 167330SN/A// static function: call resetStats() on all SimObjects. 168330SN/A// 169330SN/Avoid 170330SN/ASimObject::resetAllStats() 171330SN/A{ 172332SN/A SimObjectList::iterator i = simObjectList.begin(); 173332SN/A SimObjectList::iterator end = simObjectList.end(); 174332SN/A 175332SN/A for (; i != end; ++i) { 176332SN/A SimObject *obj = *i; 177332SN/A obj->resetStats(); 178332SN/A } 179330SN/A} 180330SN/A 181330SN/A// 182395SN/A// static function: serialize all SimObjects. 183395SN/A// 184395SN/Avoid 185395SN/ASimObject::serializeAll(ostream &os) 186395SN/A{ 187573SN/A SimObjectList::reverse_iterator ri = simObjectList.rbegin(); 188573SN/A SimObjectList::reverse_iterator rend = simObjectList.rend(); 189395SN/A 190573SN/A for (; ri != rend; ++ri) { 191573SN/A SimObject *obj = *ri; 192395SN/A obj->nameOut(os); 193395SN/A obj->serialize(os); 194395SN/A } 195395SN/A} 196843SN/A 1972797Sktlim@umich.eduvoid 1982797Sktlim@umich.eduSimObject::unserializeAll(Checkpoint *cp) 1992797Sktlim@umich.edu{ 2002797Sktlim@umich.edu SimObjectList::reverse_iterator ri = simObjectList.rbegin(); 2012797Sktlim@umich.edu SimObjectList::reverse_iterator rend = simObjectList.rend(); 2022797Sktlim@umich.edu 2032797Sktlim@umich.edu for (; ri != rend; ++ri) { 2042797Sktlim@umich.edu SimObject *obj = *ri; 2052797Sktlim@umich.edu DPRINTFR(Config, "Unserializing '%s'\n", 2062797Sktlim@umich.edu obj->name()); 2072797Sktlim@umich.edu if(cp->sectionExists(obj->name())) 2082797Sktlim@umich.edu obj->unserialize(cp, obj->name()); 2092797Sktlim@umich.edu else 2102797Sktlim@umich.edu warn("Not unserializing '%s': no section found in checkpoint.\n", 2112797Sktlim@umich.edu obj->name()); 2122797Sktlim@umich.edu } 2132797Sktlim@umich.edu} 2142797Sktlim@umich.edu 2151031SN/A#ifdef DEBUG 2161031SN/A// 2171031SN/A// static function: flag which objects should have the debugger break 2181031SN/A// 2191031SN/Avoid 2201031SN/ASimObject::debugObjectBreak(const string &objs) 2211031SN/A{ 2221031SN/A SimObjectList::const_iterator i = simObjectList.begin(); 2231031SN/A SimObjectList::const_iterator end = simObjectList.end(); 2241031SN/A 2251031SN/A ObjectMatch match(objs); 2261031SN/A for (; i != end; ++i) { 2271031SN/A SimObject *obj = *i; 2281031SN/A obj->doDebugBreak = match.match(obj->name()); 2291031SN/A } 2301031SN/A} 2311031SN/A 2321031SN/Avoid 2331031SN/AdebugObjectBreak(const char *objs) 2341031SN/A{ 2351031SN/A SimObject::debugObjectBreak(string(objs)); 2361031SN/A} 2371031SN/A#endif 2381031SN/A 239938SN/Avoid 240938SN/ASimObject::recordEvent(const std::string &stat) 241938SN/A{ 2424076Sbinkertn@umich.edu Stats::recordEvent(stat); 243938SN/A} 244938SN/A 2452901Ssaidi@eecs.umich.eduunsigned int 2462839Sktlim@umich.eduSimObject::drain(Event *drain_event) 2472797Sktlim@umich.edu{ 2482901Ssaidi@eecs.umich.edu state = Drained; 2492901Ssaidi@eecs.umich.edu return 0; 2502797Sktlim@umich.edu} 2512797Sktlim@umich.edu 2522609SN/Avoid 2532797Sktlim@umich.eduSimObject::resume() 2542609SN/A{ 2552901Ssaidi@eecs.umich.edu state = Running; 2562797Sktlim@umich.edu} 2572797Sktlim@umich.edu 2582797Sktlim@umich.eduvoid 2592797Sktlim@umich.eduSimObject::setMemoryMode(State new_mode) 2602797Sktlim@umich.edu{ 2612901Ssaidi@eecs.umich.edu panic("setMemoryMode() should only be called on systems"); 2622797Sktlim@umich.edu} 2632797Sktlim@umich.edu 2642797Sktlim@umich.eduvoid 2652797Sktlim@umich.eduSimObject::switchOut() 2662797Sktlim@umich.edu{ 2672797Sktlim@umich.edu panic("Unimplemented!"); 2682797Sktlim@umich.edu} 2692797Sktlim@umich.edu 2702797Sktlim@umich.eduvoid 2712797Sktlim@umich.eduSimObject::takeOverFrom(BaseCPU *cpu) 2722797Sktlim@umich.edu{ 2732797Sktlim@umich.edu panic("Unimplemented!"); 2742609SN/A} 2752609SN/A 276843SN/ADEFINE_SIM_OBJECT_CLASS_NAME("SimObject", SimObject) 277