sim_object.cc revision 11240
12SN/A/*
21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan
37534Ssteve.reinhardt@amd.com * Copyright (c) 2010 Advanced Micro Devices, Inc.
42SN/A * All rights reserved.
52SN/A *
62SN/A * Redistribution and use in source and binary forms, with or without
72SN/A * modification, are permitted provided that the following conditions are
82SN/A * met: redistributions of source code must retain the above copyright
92SN/A * notice, this list of conditions and the following disclaimer;
102SN/A * redistributions in binary form must reproduce the above copyright
112SN/A * notice, this list of conditions and the following disclaimer in the
122SN/A * documentation and/or other materials provided with the distribution;
132SN/A * neither the name of the copyright holders nor the names of its
142SN/A * contributors may be used to endorse or promote products derived from
152SN/A * this software without specific prior written permission.
162SN/A *
172SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
182SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
192SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
202SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
212SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
222SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
232SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
242SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
252SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
262SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
272SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
282665Ssaidi@eecs.umich.edu *
292665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt
302665Ssaidi@eecs.umich.edu *          Nathan Binkert
312SN/A */
322SN/A
336216Snate@binkert.org#include <cassert>
342SN/A
35330SN/A#include "base/callback.hh"
3656SN/A#include "base/inifile.hh"
371031SN/A#include "base/match.hh"
38330SN/A#include "base/misc.hh"
39330SN/A#include "base/trace.hh"
406214Snate@binkert.org#include "base/types.hh"
418320Ssteve.reinhardt@amd.com#include "debug/Checkpoint.hh"
4210023Smatt.horsnell@ARM.com#include "sim/probe/probe.hh"
43330SN/A#include "sim/sim_object.hh"
44695SN/A#include "sim/stats.hh"
452SN/A
462SN/Ausing namespace std;
472SN/A
482SN/A
492SN/A////////////////////////////////////////////////////////////////////////
502SN/A//
512SN/A// SimObject member definitions
522SN/A//
532SN/A////////////////////////////////////////////////////////////////////////
542SN/A
552SN/A//
562SN/A// static list of all SimObjects, used for initialization etc.
572SN/A//
582SN/ASimObject::SimObjectList SimObject::simObjectList;
592SN/A
602SN/A//
612SN/A// SimObject constructor: used to maintain static simObjectList
622SN/A//
634762Snate@binkert.orgSimObject::SimObject(const Params *p)
649983Sstever@gmail.com    : EventManager(getEventQueue(p->eventq_index)), _params(p)
652SN/A{
661031SN/A#ifdef DEBUG
671031SN/A    doDebugBreak = false;
681031SN/A#endif
691553SN/A    simObjectList.push_back(this);
7010023Smatt.horsnell@ARM.com    probeManager = new ProbeManager(this);
711553SN/A}
721553SN/A
7310422Sandreas.hansson@arm.comSimObject::~SimObject()
7410422Sandreas.hansson@arm.com{
7510422Sandreas.hansson@arm.com    delete probeManager;
7610422Sandreas.hansson@arm.com}
7710422Sandreas.hansson@arm.com
78465SN/Avoid
79465SN/ASimObject::init()
80465SN/A{
81465SN/A}
82465SN/A
837492Ssteve.reinhardt@amd.comvoid
8410905Sandreas.sandberg@arm.comSimObject::loadState(CheckpointIn &cp)
857532Ssteve.reinhardt@amd.com{
8610905Sandreas.sandberg@arm.com    if (cp.sectionExists(name())) {
878320Ssteve.reinhardt@amd.com        DPRINTF(Checkpoint, "unserializing\n");
8810905Sandreas.sandberg@arm.com        // This works despite name() returning a fully qualified name
8910905Sandreas.sandberg@arm.com        // since we are at the top level.
9010905Sandreas.sandberg@arm.com        unserializeSection(cp, name());
918320Ssteve.reinhardt@amd.com    } else {
928320Ssteve.reinhardt@amd.com        DPRINTF(Checkpoint, "no checkpoint section found\n");
938320Ssteve.reinhardt@amd.com    }
947532Ssteve.reinhardt@amd.com}
957532Ssteve.reinhardt@amd.com
967532Ssteve.reinhardt@amd.comvoid
977532Ssteve.reinhardt@amd.comSimObject::initState()
987532Ssteve.reinhardt@amd.com{
997532Ssteve.reinhardt@amd.com}
1007532Ssteve.reinhardt@amd.com
1017532Ssteve.reinhardt@amd.comvoid
1027492Ssteve.reinhardt@amd.comSimObject::startup()
1037492Ssteve.reinhardt@amd.com{
1047492Ssteve.reinhardt@amd.com}
1057492Ssteve.reinhardt@amd.com
1062SN/A//
1072SN/A// no default statistics, so nothing to do in base implementation
1082SN/A//
1092SN/Avoid
1102SN/ASimObject::regStats()
1112SN/A{
1122SN/A}
1132SN/A
1142SN/Avoid
115330SN/ASimObject::resetStats()
116330SN/A{
117330SN/A}
118330SN/A
11910023Smatt.horsnell@ARM.com/**
12010023Smatt.horsnell@ARM.com * No probe points by default, so do nothing in base.
12110023Smatt.horsnell@ARM.com */
12210023Smatt.horsnell@ARM.comvoid
12310023Smatt.horsnell@ARM.comSimObject::regProbePoints()
12410023Smatt.horsnell@ARM.com{
12510023Smatt.horsnell@ARM.com}
12610023Smatt.horsnell@ARM.com
12710023Smatt.horsnell@ARM.com/**
12810023Smatt.horsnell@ARM.com * No probe listeners by default, so do nothing in base.
12910023Smatt.horsnell@ARM.com */
13010023Smatt.horsnell@ARM.comvoid
13110023Smatt.horsnell@ARM.comSimObject::regProbeListeners()
13210023Smatt.horsnell@ARM.com{
13310023Smatt.horsnell@ARM.com}
13410023Smatt.horsnell@ARM.com
13510023Smatt.horsnell@ARM.comProbeManager *
13610023Smatt.horsnell@ARM.comSimObject::getProbeManager()
13710023Smatt.horsnell@ARM.com{
13810023Smatt.horsnell@ARM.com    return probeManager;
13910023Smatt.horsnell@ARM.com}
14010023Smatt.horsnell@ARM.com
1412SN/A//
142395SN/A// static function: serialize all SimObjects.
143395SN/A//
144395SN/Avoid
14510905Sandreas.sandberg@arm.comSimObject::serializeAll(CheckpointOut &cp)
146395SN/A{
147573SN/A    SimObjectList::reverse_iterator ri = simObjectList.rbegin();
148573SN/A    SimObjectList::reverse_iterator rend = simObjectList.rend();
149395SN/A
150573SN/A    for (; ri != rend; ++ri) {
151573SN/A        SimObject *obj = *ri;
15210905Sandreas.sandberg@arm.com        // This works despite name() returning a fully qualified name
15310905Sandreas.sandberg@arm.com        // since we are at the top level.
15411240Sandreas.sandberg@arm.com        obj->serializeSection(cp, obj->name());
155395SN/A   }
156395SN/A}
157843SN/A
1587492Ssteve.reinhardt@amd.com
1591031SN/A#ifdef DEBUG
1601031SN/A//
1611031SN/A// static function: flag which objects should have the debugger break
1621031SN/A//
1631031SN/Avoid
1641031SN/ASimObject::debugObjectBreak(const string &objs)
1651031SN/A{
1661031SN/A    SimObjectList::const_iterator i = simObjectList.begin();
1671031SN/A    SimObjectList::const_iterator end = simObjectList.end();
1681031SN/A
1691031SN/A    ObjectMatch match(objs);
1701031SN/A    for (; i != end; ++i) {
1711031SN/A        SimObject *obj = *i;
1721031SN/A        obj->doDebugBreak = match.match(obj->name());
1731031SN/A   }
1741031SN/A}
1751031SN/A
1761031SN/Avoid
1771031SN/AdebugObjectBreak(const char *objs)
1781031SN/A{
1791031SN/A    SimObject::debugObjectBreak(string(objs));
1801031SN/A}
1811031SN/A#endif
1821031SN/A
1835314Sstever@gmail.comSimObject *
1845314Sstever@gmail.comSimObject::find(const char *name)
1855314Sstever@gmail.com{
1865314Sstever@gmail.com    SimObjectList::const_iterator i = simObjectList.begin();
1875314Sstever@gmail.com    SimObjectList::const_iterator end = simObjectList.end();
1885314Sstever@gmail.com
1895314Sstever@gmail.com    for (; i != end; ++i) {
1905314Sstever@gmail.com        SimObject *obj = *i;
1915314Sstever@gmail.com        if (obj->name() == name)
1925314Sstever@gmail.com            return obj;
1935314Sstever@gmail.com    }
1945314Sstever@gmail.com
1955314Sstever@gmail.com    return NULL;
1965314Sstever@gmail.com}
197